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    Method for manufacturing semiconductor package with connection structures including via groups
    5.
    发明授权
    Method for manufacturing semiconductor package with connection structures including via groups 有权

    公开(公告)号：US11532587B2

    公开(公告)日：2022-12-20

    申请号：US17170268

    申请日：2021-02-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chien-Hsun Chen ,  Jiun Yi Wu ,  Chien-Hsun Lee ,  Chung-Shi Liu

    IPC: H01L23/00 ,  H01L25/10 ,  H01L21/56

    Abstract: A method includes placing a package component over a carrier, encapsulating the package component in an encapsulant, and forming a connection structure over and electrically coupling to the package component. The formation of the connection structure includes forming a first via group over and electrically coupling to the package component, forming a first conductive trace over and contacting the first via group, forming a second via group overlying and contacting the first conductive trace, wherein each of the first via group and the second via group comprises a plurality of vias, forming a second conductive trace over and contacting the second via group, forming a top via overlying and contacting the second conductive trace, and forming an Under-Bump-Metallurgy (UBM) over and contacting the top via.

    Package including metallic bolstering pattern and manufacturing method of the package
    6.
    发明授权
    Package including metallic bolstering pattern and manufacturing method of the package 有权

    公开(公告)号：US11177218B2

    公开(公告)日：2021-11-16

    申请号：US16824722

    申请日：2020-03-20

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jiun-Yi Wu ,  Chien-Hsun Lee ,  Shou-Yi Wang ,  Chien-Hsun Chen

    IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L21/52 ,  H01L23/00 ,  H01L21/56

    Abstract: A package has a first semiconductor die, a second semiconductor die, a redistribution structure and a metallic bolstering pattern. The second semiconductor die is disposed beside the first semiconductor die and spaced apart from the first semiconductor die with a distance. The redistribution structure is disposed over the first semiconductor die and the second semiconductor die and is electrically connected with the first and second semiconductor dies. The metallic bolstering pattern is disposed between the redistribution structure and the first and second semiconductor dies. The metallic bolstering pattern is disposed on the redistribution structure and located over the first and second semiconductor dies, and the metallic bolstering pattern extends across the distance between the first and second semiconductor dies and extends beyond borders of the first and second semiconductor dies.

    INTEGRATED CIRCUIT PACKAGE AND METHOD
    7.
    发明公开
    INTEGRATED CIRCUIT PACKAGE AND METHOD 审中-公开

    公开(公告)号：US20230260862A1

    公开(公告)日：2023-08-17

    申请号：US18302589

    申请日：2023-04-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chien-Hsun Chen ,  Yu-Ling Tsai ,  Jiun Yi Wu ,  Chien-Hsun Lee ,  Chung-Shi Liu

    IPC: H01L23/31 ,  H01L23/538 ,  H01L23/498

    CPC classification number: H01L23/3121 ,  H01L23/5384 ,  H01L23/49827

    Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.

    Method for Manufacturing Semiconductor Package with Connection Structures Including Via Groups
    8.
    发明申请
    Method for Manufacturing Semiconductor Package with Connection Structures Including Via Groups 有权

    公开(公告)号：US20230122816A1

    公开(公告)日：2023-04-20

    申请号：US18068088

    申请日：2022-12-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chien-Hsun Chen ,  Jiun Yi Wu ,  Chien-Hsun Lee ,  Chung -Shi Liu

    IPC: H01L23/00 ,  H01L25/10 ,  H01L21/56

    Abstract: A method includes placing a package component over a carrier, encapsulating the package component in an encapsulant, and forming a connection structure over and electrically coupling to the package component. The formation of the connection structure includes forming a first via group over and electrically coupling to the package component, forming a first conductive trace over and contacting the first via group, forming a second via group overlying and contacting the first conductive trace, wherein each of the first via group and the second via group comprises a plurality of vias, forming a second conductive trace over and contacting the second via group, forming a top via overlying and contacting the second conductive trace, and forming an Under-Bump-Metallurgy (UBM) over and contacting the top via.

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