-
公开(公告)号：US11785770B2
公开(公告)日：2023-10-10
申请号：US18079047
申请日：2022-12-12
Inventor： Wen-Tuo Huang , Ping-Cheng Li , Hung-Ling Shih , Po-Wei Liu , Yu-Ling Hsu , Yong-Shiuan Tsair , Chia-Sheng Lin , Shih Kuang Yang
IPC: H01L21/768 , H10B41/30 , H01L21/28 , H01L23/522 , H01L23/528 , H01L23/532 , H01L29/40 , H01L29/423 , H01L29/49 , H01L29/66 , H01L29/788
CPC classification number: H10B41/30 , H01L21/76802 , H01L21/76877 , H01L23/528 , H01L23/5226 , H01L23/53271 , H01L29/401 , H01L29/40114 , H01L29/42328 , H01L29/4916 , H01L29/66825 , H01L29/788
Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.
-
公开(公告)号：US20230377968A1
公开(公告)日：2023-11-23
申请号：US18181293
申请日：2023-03-09
Inventor： Harry-Haklay Chuang , Wei Cheng Wu , Chung-Jen Huang , Wen-Tuo Huang , Chia-Sheng Lin
IPC: H01L21/768 , H01L23/00 , H01L23/522 , H01L23/48 , H01L23/528 , H01L21/762 , H01L25/065
CPC classification number: H01L21/76898 , H01L24/08 , H01L24/80 , H01L23/5226 , H01L23/481 , H01L23/5283 , H01L23/5227 , H01L21/76232 , H01L21/7684 , H01L21/76877 , H01L21/76816 , H01L25/0657 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2224/02311 , H01L2224/0235 , H01L2224/02372 , H01L2224/02381 , H01L2225/06527 , H01L2225/06544 , H01L2225/06589 , H01L2924/1815
Abstract: A method includes forming first IC devices on a first frontside of a first semiconductor substrate and second IC devices on a second frontside of a second semiconductor substrate; forming a first contact pad over the first IC devices from the first frontside and a second contact pad over the second IC device from the second frontside; bonding the first and second contact pads such that the first and second IC devices are electrically connected; and forming a conductive structure on a first backside of the first semiconductor substrate. The conductive structure includes a through via (TV), a backside metal (BSM) feature, and a backside redistribution layer (BRDL). The TV is extending through the first semiconductor substrate and electrically connected the first and second IC devices to the BRDL, and the BSM feature is extended into a portion of the first semiconductor substrate and electrically connected to the TV.
-
公开(公告)号：US12101931B2
公开(公告)日：2024-09-24
申请号：US18354881
申请日：2023-07-19
Inventor： Wen-Tuo Huang , Ping-Cheng Li , Hung-Ling Shih , Po-Wei Liu , Yu-Ling Hsu , Yong-Shiuan Tsair , Chia-Sheng Lin , Shih Kuang Yang
IPC: H10B41/30 , H01L21/28 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H01L29/40 , H01L29/423 , H01L29/49 , H01L29/66 , H01L29/788
CPC classification number: H10B41/30 , H01L21/76802 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/53271 , H01L29/401 , H01L29/40114 , H01L29/42328 , H01L29/4916 , H01L29/66825 , H01L29/788
Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.
-
公开(公告)号：US12068032B2
公开(公告)日：2024-08-20
申请号：US18321975
申请日：2023-05-23
Inventor： Shih Kuang Yang , Ping-Cheng Li , Hung-Ling Shih , Po-Wei Liu , Wen-Tuo Huang , Yu-Ling Hsu , Yong-Shiuan Tsair , Chia-Sheng Lin
CPC classification number: G11C16/08 , G11C11/1657 , H10B12/053 , H10B41/30
Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.
-
公开(公告)号：US20230363155A1
公开(公告)日：2023-11-09
申请号：US18354881
申请日：2023-07-19
Inventor： Wen-Tuo Huang , Ping-Cheng Li , Hung-Ling Shih , Po-Wei Liu , Yu-Ling Hsu , Yong-Shiuan Tsair , Chia-Sheng Lin , Shih Kuang Yang
IPC: H10B41/30 , H01L21/28 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H01L29/40 , H01L29/423 , H01L29/49 , H01L29/66 , H01L29/788
CPC classification number: H10B41/30 , H01L29/40114 , H01L21/76802 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/53271 , H01L29/401 , H01L29/42328 , H01L29/4916 , H01L29/66825 , H01L29/788
Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.
-
Patent Agency Ranking
公开(公告)号：US11699488B2
公开(公告)日：2023-07-11
申请号：US17506904
申请日：2021-10-21
Inventor： Shih Kuang Yang , Ping-Cheng Li , Hung-Ling Shih , Po-Wei Liu , Wen-Tuo Huang , Yu-Ling Hsu , Yong-Shiuan Tsair , Chia-Sheng Lin
CPC classification number: G11C16/08 , G11C11/1657 , H10B12/053 , H10B41/30
Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.
-
公开(公告)号：US20250070092A1
公开(公告)日：2025-02-27
申请号：US18944104
申请日：2024-11-12
Inventor： Harry-Hak-Lay Chuang , Wei-Cheng Wu , Wen-Tuo Huang , Chia-Sheng Lin , Wei Chuang Wu , Shih Kuang Yang , Chung-Jen Huang , Shun-Kuan Lin , Chien Lin Liu , Ping-Tzu Chen , Yung Chun Tu
IPC: H01L25/065 , H01L23/00 , H01L25/00
Abstract: Various embodiments of the present disclosure are directed towards a shared frontside pad/bridge layout for a three-dimensional (3D) integrated circuit (IC), as well as the 3D IC and a method for forming the 3D IC. A second IC die underlies the first IC die, and a third IC die underlies the second IC die. A first-die backside pad, a second-die backside pad, and a third die backside pad are in a row extending in a dimension and overlie the first, second, and third IC dies. Further, the first-die, second-die, and third-die backside pads are electrically coupled respectively to individual semiconductor devices of the first, second, and third IC dies. The second and third IC dies include individual pad/bridge structures at top metal (TM) layers of corresponding interconnect structures. The pad/bridge structures share the shared frontside pad/bridge layout and provide lateral routing in the dimension for the aforementioned electrical coupling.
-
公开(公告)号：US12191282B2
公开(公告)日：2025-01-07
申请号：US17702068
申请日：2022-03-23
Inventor： Harry-Hak-Lay Chuang , Wei-Cheng Wu , Wen-Tuo Huang , Chia-Sheng Lin , Wei Chuang Wu , Shih Kuang Yang , Chung-Jen Huang , Shun-Kuan Lin , Chien Lin Liu , Ping-Tzu Chen , Yung Chun Tu
IPC: H01L25/065 , H01L23/00 , H01L25/00
Abstract: Various embodiments of the present disclosure are directed towards a shared frontside pad/bridge layout for a three-dimensional (3D) integrated circuit (IC), as well as the 3D IC and a method for forming the 3D IC. A second IC die underlies the first IC die, and a third IC die underlies the second IC die. A first-die backside pad, a second-die backside pad, and a third die backside pad are in a row extending in a dimension and overlie the first, second, and third IC dies. Further, the first-die, second-die, and third-die backside pads are electrically coupled respectively to individual semiconductor devices of the first, second, and third IC dies. The second and third IC dies include individual pad/bridge structures at top metal (TM) layers of corresponding interconnect structures. The pad/bridge structures share the shared frontside pad/bridge layout and provide lateral routing in the dimension for the aforementioned electrical coupling.
-
公开(公告)号：US20240373628A1
公开(公告)日：2024-11-07
申请号：US18774012
申请日：2024-07-16
Inventor： Wen-Tuo Huang , Ping-Cheng Li , Hung-Ling Shih , Po-Wei Liu , Yu-Ling Hsu , Yong-Shiuan Tsair , Chia-Sheng Lin , Shih Kuang Yang
IPC: H10B41/30 , H01L21/28 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H01L29/40 , H01L29/423 , H01L29/49 , H01L29/66 , H01L29/788
Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.
-
公开(公告)号：US20240355393A1
公开(公告)日：2024-10-24
申请号：US18760318
申请日：2024-07-01
Inventor： Shih Kuang Yang , Ping-Cheng Li , Hung-Ling Shih , Po-Wei Liu , Wen-Tuo Huang , Yu-Ling Hsu , Yong-Shiuan Tsair , Chia-Sheng Lin
CPC classification number: G11C16/08 , G11C11/1657 , H10B12/053 , H10B41/30
Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.
-
-
-
-
-
-
-
-
-
Search Results
17
records
(took 0.022 seconds)
