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    Bandgap reference circuit
    1.
    发明授权
    Bandgap reference circuit 有权

    公开(公告)号：US09876008B2

    公开(公告)日：2018-01-23

    申请号：US14458994

    申请日：2014-08-13

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chewn-Pu Jou ,  Chien-Jung Wang

    IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L29/78 ,  H01L27/07

    CPC分类号： H01L27/0617 ,  H01L27/0722 ,  H01L29/78 ,  H01L29/7838

    摘要： An integrated circuit comprises a first doped region and a second doped region in a substrate. The second doped region is separated from the first doped region by a first spacing. The integrated circuit further comprises a dielectric layer over the substrate and a gate over the dielectric layer. The gate is positioned having the first doped region on a first substrate side of the gate and the second doped region on a second substrate side of the gate opposite the first substrate side of the gate. The integrated circuit also comprises a third doped region in the substrate separated from the first doped region by a second spacing. The integrated circuit further comprises a fourth doped region in the substrate. The gate and the third doped region are coupled with a first voltage supply, and the fourth doped region is coupled with a second voltage supply.

    Seal ring structures with reduced moisture-induced reliability degradation
    3.
    发明授权
    Seal ring structures with reduced moisture-induced reliability degradation 有权
    密封环结构具有减少的水分诱导的可靠性降低

    公开(公告)号：US08729705B2

    公开(公告)日：2014-05-20

    申请号：US14132373

    申请日：2013-12-18

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chien-Jung Wang ,  Jian-Hong Lin

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening.

    摘要翻译： 半导体芯片包括与半导体芯片的边缘相邻的密封环; 从所述密封环的顶表面延伸到底表面的开口，其中所述开口具有在所述密封环的外侧上的第一端和所述密封环的内侧上的第二端; 以及具有平行于所述密封环的最近侧的侧壁的防潮屏障，其中所述防潮层邻近所述密封环并具有面向所述开口的部分。

    SEAL RING STRUCTURES WITH REDUCED MOISTURE-INDUCED RELIABILITY DEGRADATION
    4.
    发明申请
    SEAL RING STRUCTURES WITH REDUCED MOISTURE-INDUCED RELIABILITY DEGRADATION 有权
    具有降低水分诱导可靠性降解的密封环结构

    公开(公告)号：US20140103496A1

    公开(公告)日：2014-04-17

    申请号：US14132373

    申请日：2013-12-18

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chien-Jung Wang ,  Jian-Hong Lin

    IPC分类号： H01L23/58

    CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening.

    摘要翻译： 半导体芯片包括与半导体芯片的边缘相邻的密封环; 从所述密封环的顶表面延伸到底表面的开口，其中所述开口具有在所述密封环的外侧上的第一端和所述密封环的内侧上的第二端; 以及具有平行于所述密封环的最近侧的侧壁的防潮屏障，其中所述防潮层邻近所述密封环并且具有面向所述开口的部分。

    Semiconductor structure and manufacturing method thereof
    5.
    发明授权
    Semiconductor structure and manufacturing method thereof 有权

    公开(公告)号：US10475719B2

    公开(公告)日：2019-11-12

    申请号：US16023951

    申请日：2018-06-29

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： Pei-Haw Tsao ,  Chien-Jung Wang

    IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L23/00

    摘要： A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL.

    Method Of Forming An Interconnect Structure Having An Enlarged Region
    6.
    发明申请
    Method Of Forming An Interconnect Structure Having An Enlarged Region 有权
    形成具有放大区域的互连结构的方法

    公开(公告)号：US20130316073A1

    公开(公告)日：2013-11-28

    申请号：US13953418

    申请日：2013-07-29

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chien-Jung Wang

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76879 ,  H01L21/76816 ,  H01L21/76838 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming an interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce or eliminate stress induced voids between the via and the underlying conductive region. In another embodiment, one or more redundant lines are formed extending from a conductive region, such as a contact pad, such that the redundant line does not electrically couple the conductive region to an underlying conductive region. In a preferred embodiment, the redundant lines extend from a conductive region on a side adjacent to a side having a conductive line coupled to a via.

    摘要翻译： 提供了形成可以减少或消除应力引起的空隙的互连结构的方法。 在一个实施例中，通孔形成在导线下方以提供到下面的导电区域的电连接。 导线包括通孔上方的加宽区域。 加宽区域用于减少或消除通孔和下面的导电区域之间的应力诱发的空隙。 在另一个实施例中，形成从诸如接触焊盘的导电区域延伸的一条或多条冗余线，使得冗余线不将导电区域电耦合到下面的导电区域。 在优选实施例中，冗余线从与具有耦合到通孔的导线的侧面相邻的一侧上的导电区域延伸。

    Semiconductor structure and manufacturing method thereof
    7.
    发明授权
    Semiconductor structure and manufacturing method thereof 有权

    公开(公告)号：US11037849B2

    公开(公告)日：2021-06-15

    申请号：US16676053

    申请日：2019-11-06

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： Pei-Haw Tsao ,  Chien-Jung Wang

    IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L23/00

    摘要： A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL.

    Method of forming an interconnect structure having an enlarged region
    8.
    发明授权
    Method of forming an interconnect structure having an enlarged region 有权
    形成具有扩大区域的互连结构的方法

    公开(公告)号：US08785323B2

    公开(公告)日：2014-07-22

    申请号：US13953418

    申请日：2013-07-29

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chien-Jung Wang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76879 ,  H01L21/76816 ,  H01L21/76838 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming an interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce or eliminate stress induced voids between the via and the underlying conductive region. In another embodiment, one or more redundant lines are formed extending from a conductive region, such as a contact pad, such that the redundant line does not electrically couple the conductive region to an underlying conductive region. In a preferred embodiment, the redundant lines extend from a conductive region on a side adjacent to a side having a conductive line coupled to a via.

    摘要翻译： 提供了形成可以减少或消除应力引起的空隙的互连结构的方法。 在一个实施例中，通孔形成在导线下方以提供到下面的导电区域的电连接。 导线包括通孔上方的加宽区域。 加宽区域用于减少或消除通孔和下面的导电区域之间的应力诱发的空隙。 在另一个实施例中，形成从诸如接触焊盘的导电区域延伸的一条或多条冗余线，使得冗余线不将导电区域电耦合到下面的导电区域。 在优选实施例中，冗余线从与具有耦合到通孔的导线的侧面相邻的一侧上的导电区域延伸。

    Method of forming bandgap reference integrated circuit
    10.
    发明授权
    Method of forming bandgap reference integrated circuit 有权

    公开(公告)号：US10211202B2

    公开(公告)日：2019-02-19

    申请号：US15876999

    申请日：2018-01-22

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chewn-Pu Jou ,  Chien-Jung Wang

    IPC分类号： H01L29/772 ,  G05F1/46 ,  H01L27/06 ,  H01L29/78 ,  H01L27/07

    摘要： A method of forming an integrated circuit comprises forming a first doped region and a second doped region in a substrate. The second doped region is formed separate from the first doped region by a first spacing. A dielectric layer is formed over the substrate, and a gate is formed over the dielectric layer. The gate is positioned having the first doped region on a first substrate side of the gate and the second doped region on a second substrate side of the gate, opposite the first substrate side of the gate. A third doped region is formed in the substrate separated from the first doped region by a second spacing. The method further comprises forming a fourth doped region in the substrate.