公开(公告)号：US09136211B2

公开(公告)日：2015-09-15

申请号：US13946187

申请日：2013-07-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung Yu Wang ,  Chien-Hsun Lee ,  Pei-Haw Tsao ,  Kuo-Chin Chang ,  Chung-Yi Lin ,  Bill Kiang

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48647 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/207 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Protection of a solder ball joint is disclosed in which the solder ball joint is located below the surface level of the encapsulating buffer layer. The buffering layer is etched to expose one or more electrode posts, each of which may be made up of a single column or multiple columns. A top layer resulting either from a top conductive cap or a plating layer around the electrode posts also lies below the buffer layer. When the solder ball is placed onto the posts, the solder/ball joint is protected in a position below the surface of the buffer layer, while still maintaining an electrical connection between the various solder balls and their associated or capping/plating material, electrode posts, wiring layers, and circuit layers. Therefore, the entire ball joint is protected from direct stress.

Abstract translation: 公开了焊球接头的保护，其中焊球接头位于封装缓冲层的表面水平以下。 蚀刻缓冲层以露出一个或多个电极柱，每个电极柱可以由单个柱或多个柱组成。 由顶部导电盖或电极柱周围的镀层产生的顶层也位于缓冲层的下方。 当焊球放置在柱上时，焊料/球窝接头被保护在缓冲层表面下方的位置，同时仍然保持各种焊球之间的电连接及其相关或封盖/电镀材料，电极柱 ，布线层和电路层。 因此，保护​​整个球窝接头免受直接的压力。

公开(公告)号：US11804445B2

公开(公告)日：2023-10-31

申请号：US17244754

申请日：2021-04-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Heh-Chang Huang ,  Fu-Jen Li ,  Pei-Haw Tsao ,  Shyue-Ter Leu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214

Abstract: A chip package structure is provided. The chip package structure includes a first chip structure including a substrate and an interconnect layer over the substrate. The chip package structure includes a second chip structure over the interconnect layer. The chip package structure includes a first conductive bump connected between the interconnect layer and the second chip structure. The chip package structure includes a conductive pillar over the interconnect layer. The chip package structure includes a molding layer over the interconnect layer and surrounding the second chip structure, the first conductive bump, and the conductive pillar. The chip package structure includes a second conductive bump over a first surface of the conductive pillar. The first surface faces away from the first chip structure.

公开(公告)号：US11798860B2

公开(公告)日：2023-10-24

申请号：US17344827

申请日：2021-06-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Pei-Haw Tsao ,  Chien-Jung Wang

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/3185 ,  H01L21/56 ,  H01L24/02 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02377 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/10126 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/10156 ,  H01L2924/3512 ,  H01L2224/1132 ,  H01L2924/00014 ,  H01L2224/11334 ,  H01L2924/00014 ,  H01L2224/11849 ,  H01L2924/00014 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2224/94 ,  H01L2224/11

Abstract: A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL.

公开(公告)号：US11239143B2

公开(公告)日：2022-02-01

申请号：US16532216

申请日：2019-08-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Pei-Haw Tsao ,  Tsung-Hsing Lu ,  Li-Huan Chu

IPC: H01L23/498 ,  H05K1/02 ,  H01L21/48

Abstract: A semiconductor structure includes a first substrate including a first surface and a second surface opposite to the first surface; a first conductive via extended through the first substrate; a second conductive via extended through the first substrate; and a third conductive via extended through the first substrate, wherein the second conductive via is disposed between the first conductive via and the third conductive via, the second conductive via is configured to connect to a signal source, and the first conductive via and the third conductive via are configured to connect to an electrical ground.

公开(公告)号：US09780046B2

公开(公告)日：2017-10-03

申请号：US14940920

申请日：2015-11-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Yu Pan ,  Han-Ping Pu ,  Pei-Haw Tsao ,  Yu-Chen Hsu

IPC: H01L21/02 ,  H01L23/58 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/585 ,  H01L21/563 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/562 ,  H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/02373 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05583 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/06133 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/351 ,  H01L2924/35121

Abstract: An embodiment device includes a semiconductor substrate and an interconnect structure over the semiconductor substrate. The interconnect structure includes a functional circuit region and a first portion of a seal ring spaced apart from the functional circuit region by a buffer zone. The device also includes a passivation layer over the interconnect structure and a second portion of the seal ring over the passivation layer and connected the first portion of the seal ring. The second portion of the seal ring is disposed in the buffer zone.

公开(公告)号：US12230593B2

公开(公告)日：2025-02-18

申请号：US17389610

申请日：2021-07-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kai-Heng Chen ,  Pei-Haw Tsao ,  Shyue-Ter Leu ,  Rung-De Wang ,  Chien-Chun Wang

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/58

Abstract: A package structure is provided, including a substrate, a first passivation layer, a metallization layer, a second passivation layer, and a polymer layer. The first passivation layer is formed over the substrate. The metallization layer is conformally formed on the first passivation layer. The second passivation layer is conformally formed on the first passivation layer and the metallization layer. A step structure is formed on the top surface of the second passivation layer, and includes at least one lower part that is lower than the other parts of the step structure. The polymer layer is formed over the second passivation layer. A portion of the polymer layer extends into the lower part of the step structure to engage with the step structure.

公开(公告)号：US11978729B2

公开(公告)日：2024-05-07

申请号：US17370282

申请日：2021-07-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Heh-Chang Huang ,  Fu-Jen Li ,  Pei-Haw Tsao ,  Shyue-Ter Leu

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/16 ,  H01L21/563 ,  H01L23/3135 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203

Abstract: A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a package substrate having a first surface and a second surface opposite to the first surface. Several integrated devices are bonded to the first surface of the package substrate. A first underfill element is disposed over the first surface and surrounds the integrated devices. A first molding layer is disposed over the first surface and surrounds the integrated devices and the first underfill element. A semiconductor die is bonded to the second surface of the package substrate. A second underfill element is disposed over the second surface and surrounds the semiconductor die. A second molding layer is disposed over the second surface and surrounds the semiconductor die and the second underfill element. Several conductive bumps are disposed over the second surface and adjacent to the second molding layer.

公开(公告)号：US11495556B2

公开(公告)日：2022-11-08

申请号：US16205705

申请日：2018-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Pei-Haw Tsao ,  An-Tai Xu ,  Huang-Ting Hsiao ,  Kuo-Chin Chang

IPC: H01L23/14 ,  H01L23/498 ,  H01L23/532 ,  H01L23/31 ,  H01L23/00

Abstract: A method for fabricating a semiconductor structure is provided. The method includes: providing a semiconductor chip comprising an active surface; forming a conductive bump over the active surface of the semiconductor chip; and coupling the conductive bump to a substrate. The conductive bump includes a plurality of bump segments including a first group of bump segments and a second group of bump segments. Each bump segment has a same segment thickness in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment has a volume defined by a multiplication of the same segment thickness with an average cross-sectional area of the bump segment in a plane parallel to the active surface of the semiconductor chip. A ratio of a total volume of the first group of bump segments to a total volume of the second group of bump segments is between 0.03 and 0.8.

公开(公告)号：US11037849B2

公开(公告)日：2021-06-15

申请号：US16676053

申请日：2019-11-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Pei-Haw Tsao ,  Chien-Jung Wang

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL.

公开(公告)号：US11018099B2

公开(公告)日：2021-05-25

申请号：US14554788

申请日：2014-11-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Pei-Haw Tsao ,  An-Tai Xu ,  Huang-Ting Hsiao ,  Kuo-Chin Chang

IPC: H01L23/14 ,  H01L23/498 ,  H01L23/00 ,  H01L23/532 ,  H01L23/31

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a semiconductor chip; a substrate facing an active surface of the semiconductor chip; and a conductive bump extending from the active surface of the semiconductor chip toward the substrate, wherein the conductive bump comprises: a plurality of bump segments comprising a first group of bump segments and a second group of bump segments, wherein each bump segment comprises the same segment height in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment comprises a volume defined by the multiplication of the segment height with the average cross-sectional area of the bump segment; wherein the ratio of the total volume of the first group of bump segments to the total volume of the second group of bump segments is between about 0.03 and about 0.8.