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公开(公告)号：US12132477B2
公开(公告)日：2024-10-29
申请号：US18448008
申请日：2023-08-10
IPC分类号： H03K17/687 , H03K19/0175 , H03K19/0185 , H03K19/20
CPC分类号： H03K17/6872 , H03K17/6874 , H03K19/017509 , H03K19/018521 , H03K19/20
摘要： A device including an inverter circuit, a hysteresis control circuit, and a high-side input level shifter. The inverter circuit having an output and including at least two series connected PMOS transistors connected, at the output, in series to at least two series connected NMOS transistors. The hysteresis control circuit coupled to the output to provide feedback to the at least two series connected PMOS transistors and to the at least two series connected NMOS transistors. The high-side input level shifter connected to gates of the at least two PMOS transistors and configured to shift a low level of an input signal to a higher level and provide the higher level to one or more of the gates of the at least two PMOS transistors.
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公开(公告)号：US12119815B2
公开(公告)日：2024-10-15
申请号：US17581589
申请日：2022-01-21
IPC分类号： H03K17/687 , H03K19/0175 , H03K19/0185 , H03K19/20
CPC分类号： H03K17/6872 , H03K17/6874 , H03K19/017509 , H03K19/018521 , H03K19/20
摘要： A device including an inverter circuit, a hysteresis control circuit, and a high-side input level shifter. The inverter circuit having an output and including at least two series connected PMOS transistors connected, at the output, in series to at least two series connected NMOS transistors. The hysteresis control circuit coupled to the output to provide feedback to the at least two series connected PMOS transistors and to the at least two series connected NMOS transistors. The high-side input level shifter connected to gates of the at least two PMOS transistors and configured to shift a low level of an input signal to a higher level and provide the higher level to one or more of the gates of the at least two PMOS transistors.
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公开(公告)号：US11996856B2
公开(公告)日：2024-05-28
申请号：US18066245
申请日：2022-12-14
CPC分类号： H03M1/08 , H03K5/24 , H03M1/1071
摘要： The present disclosure provides a circuitry. The circuitry includes a comparator and a signal correlated circuit. The comparator includes a first input terminal, a second input terminal, and an output terminal. The signal correlated circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal is coupled to receive a first input signal. The second input terminal is coupled to receive a second input signal independent from the first input signal. The first output terminal is configured to generate a first output signal and to send the first output signal to the first input terminal of the comparator. The second output terminal is configured to generate a second output signal and to send the second output signal to the second input terminal of the comparator. The first output signal and the second output signal are correlated.
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公开(公告)号：US20240078370A1
公开(公告)日：2024-03-07
申请号：US18447916
申请日：2023-08-10
发明人： Chih-Chiang Chang , Wen-Shen Chou , Yung-Chow Peng , Yung-Hsu Chuang , Yu-Tao Yang , Bindu Madhavi Kasina
IPC分类号： G06F30/392 , G06F30/398
CPC分类号： G06F30/392 , G06F30/398 , G06F2119/18
摘要： Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells.
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公开(公告)号：US11552205B2
公开(公告)日：2023-01-10
申请号：US17096961
申请日：2020-11-13
发明人： Chih-Chiang Chang , Chia-Chan Chen
IPC分类号： H01L31/101 , H01L31/0232 , H01L31/18 , H01L31/103 , H01L31/0352
摘要： Disclosed are devices for optical sensing and manufacturing method thereof. In one embodiment, a device for optical sensing includes a substrate, a photodetector and a reflector. The photodetector is disposed in the substrate. The reflector is disposed in the substrate and spaced apart from the photodetector, wherein the reflector has a reflective surface inclined relative to the photodetector that reflects light transmitted thereto to the photodetector.
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公开(公告)号：US20220367737A1
公开(公告)日：2022-11-17
申请号：US17874276
申请日：2022-07-26
发明人： Chih-Chiang Chang , Chia-Chan Chen
IPC分类号： H01L31/0232 , H01L31/18 , H01L31/103 , H01L31/0352
摘要： Disclosed are devices for optical sensing and manufacturing method thereof. In one embodiment, a device for optical sensing includes a substrate, a photodetector and a reflector. The photodetector is disposed in the substrate. The reflector is disposed in the substrate and spaced apart from the photodetector, wherein the reflector has a reflective surface inclined relative to the photodetector that reflects light transmitted thereto to the photodetector.
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公开(公告)号：US09921254B2
公开(公告)日：2018-03-20
申请号：US14724258
申请日：2015-05-28
发明人： Yung-Chow Peng , Chih-Chiang Chang , Wen-Shen Chou , Brady Yang
CPC分类号： G01R27/28 , H03F3/45475 , H03F2200/261 , H03F2203/45514
摘要： A circuit for measuring a bandwidth of an amplifier includes a switch-capacitor circuit and a controller. The switch-capacitor circuit is coupled to an output and an input of the amplifier. The switch-capacitor circuit is switchable between a sampling mode and an amplification mode. The controller is coupled to the switch-capacitor circuit and the output of the amplifier. The controller is configured to switch the switch-capacitor circuit between the sampling mode and the amplification mode, control the amplification mode to have various durations, and determine the bandwidth of the amplifier based on the various durations of the amplification mode and corresponding voltages at the output of the amplifier.
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公开(公告)号：US12117489B2
公开(公告)日：2024-10-15
申请号：US17019239
申请日：2020-09-12
IPC分类号： G01R31/317 , G01R27/26 , G01R31/10 , H03B27/00 , H03L7/00
CPC分类号： G01R31/31727 , G01R27/2605 , G01R27/2617 , G01R31/10 , H03B27/00 , H03L7/00
摘要： A device for measuring characteristics of a wafer is provided. The device includes a first circuit on the wafer and having a first number of parallelly connected oscillators, and a second circuit on the wafer and having the first number of parallelly connected oscillators; wherein a first portion of the second circuit is disconnected from a second portion of the second circuit.
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公开(公告)号：US11816414B2
公开(公告)日：2023-11-14
申请号：US17815095
申请日：2022-07-26
发明人： Chih-Chiang Chang , Wen-Shen Chou , Yung-Chow Peng , Yung-Hsu Chuang , Yu-Tao Yang , Bindu Madhavi Kasina
IPC分类号： G06F30/392 , G06F30/398 , G06F119/18 , G06F30/31
CPC分类号： G06F30/392 , G06F30/398 , G06F30/31 , G06F2119/18
摘要： Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells.
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公开(公告)号：US20220158006A1
公开(公告)日：2022-05-19
申请号：US17096961
申请日：2020-11-13
发明人： Chih-Chiang Chang , Chia-Chan Chen
IPC分类号： H01L31/0232 , H01L31/0352 , H01L31/103 , H01L31/18
摘要： Disclosed are devices for optical sensing and manufacturing method thereof. In one embodiment, a device for optical sensing includes a substrate, a photodetector and a reflector. The photodetector is disposed in the substrate. The reflector is disposed in the substrate and spaced apart from the photodetector, wherein the reflector has a reflective surface inclined relative to the photodetector that reflects light transmitted thereto to the photodetector.
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