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公开(公告)号:US20220358273A1
公开(公告)日:2022-11-10
申请号:US17815095
申请日:2022-07-26
发明人: Chih-Chiang Chang , Wen-Shen Chou , Yung-Chow Peng , Yung-Hsu Chuang , Yu-Tao Yang , Bindu Madhavi Kasina
IPC分类号: G06F30/392 , G06F30/398
摘要: Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells.
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公开(公告)号:US20140145749A1
公开(公告)日:2014-05-29
申请号:US13926596
申请日:2013-06-25
发明人: Tsung-Hsiung Lee , Kuang-Kai Yen , Shi-Hung Wang , Yung-Hsu Chuang , Huan-Neng Chen , Wei-Li Chen , Shih-Hung Lan , Yi-Hsuan Liu , Fan-Ming Kuo , Hsieh-Hung Hsieh , Chewn-Pu Jou , Fu-Lung Hsueh
IPC分类号: G01R31/265
CPC分类号: G06K7/0095 , G01R31/2656 , G01R31/3025
摘要: A semiconductor wafer includes a plurality of dies. Each of the plurality of dies includes a radio frequency identification (RFID) tag circuit and a coil. The RFID tag circuit includes a tag core, an RF front-end circuit, an ID decoder, a comparator and conductive line for a unique ID. The RF front-end circuit is configured to receive electromagnetic signals through the coil in each of the plurality of dies and to convert the received electromagnetic signals into commands. The ID decoder is configured to receive the commands and to generate an expect ID. The comparator is configured to compare the unique ID with the expect ID to generate a comparison result. The comparison result is arranged to decide if the tag core is configured to receive commands.
摘要翻译: 半导体晶片包括多个管芯。 多个模具中的每一个都包括射频识别(RFID)标签电路和线圈。 RFID标签电路包括标签芯,RF前端电路,ID解码器,用于唯一ID的比较器和导线。 RF前端电路被配置为通过多个管芯中的每一个中的线圈接收电磁信号,并将接收到的电磁信号转换为命令。 ID解码器被配置为接收命令并产生期望ID。 比较器被配置为将唯一ID与期望ID进行比较以产生比较结果。 布置比较结果来确定标签核心是否配置为接收命令。
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公开(公告)号:US12106031B2
公开(公告)日:2024-10-01
申请号:US17460648
申请日:2021-08-30
发明人: Yung-Hsu Chuang , Wen-Shen Chou , Yung-Chow Peng , Yu-Tao Yang , Yun-Ru Chen
IPC分类号: G06F30/39 , G03F1/36 , G03F1/82 , G06F30/398
CPC分类号: G06F30/398 , G03F1/36 , G03F1/82
摘要: A semiconductor device including a first active region having a first active configuration, a second active region having a second, and different, active configuration, and a transition cell arranged between the first and second active regions in which the transition cell has a transitional configuration that is different from and compatible with both the first active configuration and the second active configuration.
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公开(公告)号:US20240078370A1
公开(公告)日:2024-03-07
申请号:US18447916
申请日:2023-08-10
发明人: Chih-Chiang Chang , Wen-Shen Chou , Yung-Chow Peng , Yung-Hsu Chuang , Yu-Tao Yang , Bindu Madhavi Kasina
IPC分类号: G06F30/392 , G06F30/398
CPC分类号: G06F30/392 , G06F30/398 , G06F2119/18
摘要: Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells.
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公开(公告)号:US11816414B2
公开(公告)日:2023-11-14
申请号:US17815095
申请日:2022-07-26
发明人: Chih-Chiang Chang , Wen-Shen Chou , Yung-Chow Peng , Yung-Hsu Chuang , Yu-Tao Yang , Bindu Madhavi Kasina
IPC分类号: G06F30/392 , G06F30/398 , G06F119/18 , G06F30/31
CPC分类号: G06F30/392 , G06F30/398 , G06F30/31 , G06F2119/18
摘要: Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells.
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公开(公告)号:US11106854B2
公开(公告)日:2021-08-31
申请号:US16460378
申请日:2019-07-02
发明人: Yung-Hsu Chuang , Wen-Shen Chou , Yung-Chow Peng , Yu-Tao Yang , Yun-Ru Chen
IPC分类号: G06F30/398 , G03F1/82 , G03F1/36
摘要: A method including the operations of receiving a preliminary device layout including a plurality of active areas, analyzing the preliminary device layout to identify empty areas between the plurality of active areas, determining the configurations of the active areas bordering the empty areas, selecting a transition cell from a transition cell library in which the transition cell has a transitional configuration for reducing density gradient effects in the active areas adjacent the transition cell, and inserting the transition cells into the empty areas to define a modified device layout.
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公开(公告)号:US11429775B1
公开(公告)日:2022-08-30
申请号:US17212499
申请日:2021-03-25
发明人: Chih-Chiang Chang , Wen-Shen Chou , Yung-Chow Peng , Yung-Hsu Chuang , Yu-Tao Yang , Bindu Madhavi Kasina
IPC分类号: G06F30/392 , G06F30/398 , G06F119/18 , G06F30/31
摘要: Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells.
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公开(公告)号:US11270057B1
公开(公告)日:2022-03-08
申请号:US16991929
申请日:2020-08-12
发明人: Yu-Tao Yang , Yung-Hsu Chuang , Wen-Shen Chou , Yung-Chow Peng
IPC分类号: G06F30/30 , G06F30/398 , G06F30/3953 , G06F30/392 , G06F117/12
摘要: A method includes: generating a design layout according to a circuit design by placing first and second components; identifying a first area and a second area between the first component and the second component; and determining a first cell configuration of the first component according to the first component and a second cell configuration of the second component according to the second component. The method further includes selecting a first cell comprising a first capacitor from a cell library, wherein the first cell has a third cell configuration identical to the first cell configuration; selecting a second cell comprising a second capacitor from the cell library, wherein the second cell has a fourth cell configuration identical to the second cell configuration; placing a first cell array formed of the first cell in the first area; and placing a second cell array formed of the second cell in the second area.
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9.
公开(公告)号:US10860777B1
公开(公告)日:2020-12-08
申请号:US16443055
申请日:2019-06-17
发明人: Yung-Hsu Chuang , Wen-Shen Chou , Jie-Ren Huang , Yu-Tao Yang , Yung-Chow Peng , Yun-Ru Chen
IPC分类号: G06F17/50 , G06F30/398 , G06F30/36 , G06F30/327 , G06F30/367 , G06F30/392 , G06F30/394
摘要: A method for fabricating a semiconductor structure is provided. The method includes assigning a set of parameter values to a set of size parameters of a unit cell of the integrated circuit in a unit cell schematic of the unit cell according to a predetermined criterion, wherein the unit cell characterized by the set of parameter values has a circuit characteristic meeting the predetermined criterion; generating a unit cell layout of the unit cell according to the unit cell schematic; generating a circuit layout comprising a plurality of replicas of the unit cell layout, the replicas of the unit cell layout being arranged in correspondence with circuit blocks in a circuit floorplan of the integrated circuit, respectively; and fabricating the integrated circuit according to the circuit layout.
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公开(公告)号:US09098757B2
公开(公告)日:2015-08-04
申请号:US13926596
申请日:2013-06-25
发明人: Tsung-Hsiung Lee , Kuang-Kai Yen , Shi-Hung Wang , Yung-Hsu Chuang , Huan-Neng Chen , Wei-Li Chen , Shih-Hung Lan , Yi-Hsuan Liu , Fan-Ming Kuo , Hsieh-Hung Hsieh , Chewn-Pu Jou , Fu-Lung Hsueh
IPC分类号: G01R31/26 , G06K7/00 , G01R31/265 , G01R31/302
CPC分类号: G06K7/0095 , G01R31/2656 , G01R31/3025
摘要: A semiconductor wafer includes a plurality of dies. Each of the plurality of dies includes a radio frequency identification (RFID) tag circuit and a coil. The RFID tag circuit includes a tag core, an RF front-end circuit, an ID decoder, a comparator and conductive line for a unique ID. The RF front-end circuit is configured to receive electromagnetic signals through the coil in each of the plurality of dies and to convert the received electromagnetic signals into commands. The ID decoder is configured to receive the commands and to generate an expect ID. The comparator is configured to compare the unique ID with the expect ID to generate a comparison result. The comparison result is arranged to decide if the tag core is configured to receive commands.
摘要翻译: 半导体晶片包括多个管芯。 多个管芯中的每一个都包括射频识别(RFID)标签电路和线圈。 RFID标签电路包括标签芯,RF前端电路,ID解码器,用于唯一ID的比较器和导线。 RF前端电路被配置为通过多个管芯中的每一个中的线圈接收电磁信号,并将接收到的电磁信号转换为命令。 ID解码器被配置为接收命令并产生期望ID。 比较器被配置为将唯一ID与期望ID进行比较以产生比较结果。 布置比较结果来确定标签核心是否配置为接收命令。
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