公开(公告)号：US20230343637A1

公开(公告)日：2023-10-26

申请号：US17660518

申请日：2022-04-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ying-Yu LAI ,  Chih-Yun WANG ,  Chih-Hsuan LIN ,  Hsi Chung CHEN

IPC: H01L21/768 ,  H01L29/417 ,  H01L29/40 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/76814 ,  H01L29/41775 ,  H01L29/401 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/823475 ,  H01L21/31122 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/02063 ,  H01L29/41791 ,  H01L29/42392

Abstract: Multiple dry etching operations are performed to form an opening for an interconnect structure, with a wet cleaning operation performed in between the dry etching operations. This multi-step etch approach increases the effectiveness of residual material removal, which increases the quality of the interconnect structure and reduces the likelihood of under etching, both of which increase semiconductor device yield and semiconductor device performance.

公开(公告)号：US20240203885A1

公开(公告)日：2024-06-20

申请号：US18590215

申请日：2024-02-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hsuan LIN ,  Hsi Chung CHEN ,  Ji-Ling WU ,  Chih-Teng LIAO

IPC: H01L23/535 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/535 ,  H01L21/32136 ,  H01L21/76805 ,  H01L21/76819 ,  H01L21/76825 ,  H01L21/76895 ,  H01L23/5283 ,  H01L23/53257

Abstract: A method of manufacturing a semiconductor device includes forming a first dielectric layer over a substrate, forming a metal layer in the first dielectric layer, forming an etch stop layer on a surface of the first dielectric layer and the metal layer, removing portions of the metal layer and the etch stop layer to form a recess in the metal layer, and forming a tungsten plug in the recess. The recess is spaced apart from a bottom surface of the etch stop layer.

公开(公告)号：US20230065056A1

公开(公告)日：2023-03-02

申请号：US17460833

申请日：2021-08-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsiao-Chien LIN ,  Hsi Chung CHEN ,  Cheng-Hung TSAI ,  Chih-Hsuan LIN

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/40

Abstract: A method includes forming a dummy gate structure across a fin, in which the dummy gate structure has a dummy gate dielectric layer and a dummy gate electrode, forming gate spacers on sidewalls of the dummy gate structure, forming source/drain epitaxial structures on sides of the dummy gate structure, performing a first etch process to the dummy gate electrode such that a recessed dummy gate electrode remains over the fin, performing a second etch process to the gate spacers such that recessed gate spacers remain over the sidewalls of the dummy gate structure, removing the recessed dummy gate electrode and the dummy gate dielectric layer after the second etch process to form a recess between the recessed gate spacers, forming a gate structure overfilling the recess, and performing a third etch process to the gate structure such that a recessed gate structure remains between the recessed gate spacers.