公开(公告)号：US20240237551A1

公开(公告)日：2024-07-11

申请号：US18615459

申请日：2024-03-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Han-Ting Lin ,  Sin-Yi Yang ,  Yu-Shu Chen ,  An-Shen Chang ,  Qiang Fu ,  Chen-Jung Wang

IPC: H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/80 ,  G11C11/161 ,  H10B61/20 ,  H10N50/01 ,  G11C11/1655 ,  G11C11/1657 ,  H10N50/85

Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.

公开(公告)号：US20210226118A1

公开(公告)日：2021-07-22

申请号：US16746158

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Han-Ting Lin ,  Sin-Yi Yang ,  Yu-Shu Chen ,  An-Shen Chang ,  Qiang Fu ,  Chen-Jung Wang

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16

Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.

公开(公告)号：US12114511B2

公开(公告)日：2024-10-08

申请号：US17462577

申请日：2021-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hui-Hsien Wei ,  Yen-Chung Ho ,  Chia-Jung Yu ,  Yong-Jie Wu ,  Pin-Cheng Hsu

IPC: H01L29/82 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80

CPC classification number: H10B61/22 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80

Abstract: A semiconductor device, an integrated circuit, and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a thin-film transistor (TFT) over the substrate, and a magnetoresistive random-access memory (MRAM) cell electrically coupled to the TFT. The TFT includes a gate electrode; a gate dielectric layer disposed over the gate electrode; source/drain electrodes disposed above the gate electrode; and an active layer disposed above the gate electrode. A protection layer is disposed between the TFT and the MRAM cell and electrically connects the MRAM cell to the TFT.

公开(公告)号：US11968908B2

公开(公告)日：2024-04-23

申请号：US17854289

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Han-Ting Lin ,  Sin-Yi Yang ,  Yu-Shu Chen ,  An-Shen Chang ,  Qiang Fu ,  Chen-Jung Wang

IPC: H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/80 ,  G11C11/161 ,  H10B61/20 ,  H10N50/01 ,  G11C11/1655 ,  G11C11/1657 ,  H10N50/85

Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.

公开(公告)号：US12178051B2

公开(公告)日：2024-12-24

申请号：US18228210

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hui-Hsien Wei ,  Chung-Te Lin ,  Han-Ting Tsai ,  Tai-Yen Peng ,  Yu-Teng Dai ,  Chien-Min Lee ,  Sheng-Chih Lai ,  Wei-Chih Wen

IPC: H10B61/00 ,  B82Y25/00 ,  G11C11/16 ,  H01F41/30 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed. The MRAM cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode. A first insulating cover layer is formed over the MRAM cell structure. A second insulating cover layer is formed over the first insulating cover layer. An interlayer dielectric (ILD) layer is formed. A contact opening in the ILD layer is formed, thereby exposing the second insulating cover layer. A part of the second insulating cover layer and a part of the first insulating cover layer are removed, thereby exposing the top electrode. A conductive layer is formed in the opening contacting the top electrode.

公开(公告)号：US20220336727A1

公开(公告)日：2022-10-20

申请号：US17854289

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Han-Ting Lin ,  Sin-Yi Yang ,  Yu-Shu Chen ,  An-Shen Chang ,  Qiang Fu ,  Chen-Jung Wang

IPC: H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  H01L43/12

Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.

公开(公告)号：US11805658B2

公开(公告)日：2023-10-31

申请号：US17537119

申请日：2021-11-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hui-Hsien Wei ,  Chung-Te Lin ,  Han-Ting Tsai ,  Tai-Yen Peng ,  Yu-Teng Dai ,  Chien-Min Lee ,  Sheng-Chih Lai ,  Wei-Chih Wen

IPC: H10B61/00 ,  G11C11/16 ,  H01F41/30 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85 ,  B82Y25/00

CPC classification number: H10B61/00 ,  G11C11/161 ,  H01F41/307 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85 ,  B82Y25/00 ,  H10B61/22

Abstract: In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed. The MRAM cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode. A first insulating cover layer is formed over the MRAM cell structure. A second insulating cover layer is formed over the first insulating cover layer. An interlayer dielectric (ILD) layer is formed. A contact opening in the ILD layer is formed, thereby exposing the second insulating cover layer. A part of the second insulating cover layer and a part of the first insulating cover layer are removed, thereby exposing the top electrode. A conductive layer is formed in the opening contacting the top electrode.

公开(公告)号：US11387406B2

公开(公告)日：2022-07-12

申请号：US16746158

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Han-Ting Lin ,  Sin-Yi Yang ,  Yu-Shu Chen ,  An-Shen Chang ,  Qiang Fu ,  Chen-Jung Wang

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16 ,  H01L43/10

Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.