公开(公告)号：US20240194523A1

公开(公告)日：2024-06-13

申请号：US18582746

申请日：2024-02-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsi-Wen Tien ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L27/092

CPC分类号： H01L21/76831 ,  H01L21/76813 ,  H01L23/5226 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/7684 ,  H01L27/092

摘要： In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes an interconnect dielectric layer over a substrate. An interconnect via is within the interconnect dielectric layer, and an interconnect wire is over the interconnect via and within the interconnect dielectric layer. A protective layer surrounds the interconnect via. The interconnect via vertically extends through the protective layer to below a bottom of the protective layer. The protective layer continuously extends from along an outer sidewall of the interconnect via to along an outer sidewall of the interconnect wire in a first cross-sectional view.

公开(公告)号：US11854965B2

公开(公告)日：2023-12-26

申请号：US17834204

申请日：2022-06-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Teng Dai ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Hsi-Wen Tien ,  Wei-Hao Liao

IPC分类号： H01L21/00 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76829 ,  H01L23/528 ,  H01L23/53295

摘要： Some embodiments relate to a method for forming a semiconductor structure, the method includes forming a first dielectric layer over a substrate. A first conductive wire is formed over the first dielectric layer. A spacer structure is formed over the first conductive wire. The spacer structure is disposed along sidewalls of the first conductive wire. A second dielectric layer is deposited over and around the first conductive wire. The spacer structure is spaced between the first conductive wire and the second dielectric layer. A removal process is performed on the spacer structure and the second dielectric layer. An upper surface of the spacer structure is disposed above an upper surface of the first conductive wire.

公开(公告)号：US20230369231A1

公开(公告)日：2023-11-16

申请号：US18360066

申请日：2023-07-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Chieh Yao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Wei-Hao Liao ,  Yu-Teng Dai ,  Hsin-Yen Huang ,  Chia-Tien Wu

IPC分类号： H01L23/538 ,  H01L21/768 ,  H01L21/48 ,  H01L23/532

CPC分类号： H01L23/5384 ,  H01L21/76802 ,  H01L21/486 ,  H01L23/5386 ,  H01L21/7682 ,  H01L23/5329

摘要： The present disclosure relates to an integrated chip comprising a substrate. A first conductive wire is over the substrate. A second conductive wire is over the substrate and is adjacent to the first conductive wire. A first dielectric cap is laterally between the first conductive wire and the second conductive wire. The first dielectric cap laterally separates the first conductive wire from the second conductive wire. The first dielectric cap includes a first dielectric material. A first cavity is directly below the first dielectric cap and is laterally between the first conductive wire and the second conductive wire. The first cavity is defined by one or more surfaces of the first dielectric cap.

公开(公告)号：US20230275028A1

公开(公告)日：2023-08-31

申请号：US18311308

申请日：2023-05-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Chieh Yao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC分类号： H01L23/535 ,  H01L21/768

CPC分类号： H01L23/535 ,  H01L21/76895 ,  H01L21/76805 ,  H01L21/76802

摘要： In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a dielectric on wire structure is arranged directly over the interconnect wire. Outer sidewalls of the dielectric on wire structure are surrounded by the first interconnect dielectric layer. The integrated chip further includes a second interconnect dielectric layer arranged over the first interconnect dielectric layer, and an interconnect via that extends through the second interconnect dielectric layer and the dielectric on wire structure to contact the interconnect wire.

公开(公告)号：US20220359368A1

公开(公告)日：2022-11-10

申请号：US17313217

申请日：2021-05-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-Hao Liao ,  Hsi-Wen Tien ,  Yu-Teng Dai ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Chung-Ju Lee

IPC分类号： H01L23/528 ,  H01L23/532 ,  H01L21/768

摘要： An interconnect structure includes dielectric layer, a first conductive feature, a second conductive feature, a third conductive feature, and a dielectric fill. The first conductive feature is disposed in the dielectric layer. The second conductive feature is disposed over the first conductive feature. The second conductive feature includes a first conductive layer disposed over the first conductive feature, a second conductive layer disposed on the first conductive layer, and a third conductive layer disposed on the second conductive layer. The first conductive layer, the second conductive layer and the third conductive layer have substantially the same width. The third conductive feature is disposed over the dielectric layer. The dielectric fill is disposed over the dielectric layer between the second conductive feature and the third conductive feature.

公开(公告)号：US20220336263A1

公开(公告)日：2022-10-20

申请号：US17855060

申请日：2022-06-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsi-Wen Tien ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Shau-Lin Shue ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H01L21/8234

摘要： The present disclosure relates to an integrated chip. The integrated chip comprises a dielectric layer over a substrate. A first metal feature is over the dielectric layer. A second metal feature is over the dielectric layer and is laterally adjacent to the first metal feature. A first dielectric liner segment extends laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer. The first dielectric liner segment extends continuously from along the upper surface of the dielectric layer, to along a sidewall of the first metal feature that faces the second metal feature, and to along a sidewall of the second metal feature that faces the first metal feature. A first cavity is laterally between sidewalls of the first dielectric liner segment and is above an upper surface of the first dielectric liner segment.

公开(公告)号：US12125795B2

公开(公告)日：2024-10-22

申请号：US18360066

申请日：2023-07-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Chieh Yao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Wei-Hao Liao ,  Yu-Teng Dai ,  Hsin-Yen Huang ,  Chia-Tien Wu

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/5384 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/7682 ,  H01L23/5329 ,  H01L23/5386

摘要： The present disclosure relates to an integrated chip comprising a substrate. A first conductive wire is over the substrate. A second conductive wire is over the substrate and is adjacent to the first conductive wire. A first dielectric cap is laterally between the first conductive wire and the second conductive wire. The first dielectric cap laterally separates the first conductive wire from the second conductive wire. The first dielectric cap includes a first dielectric material. A first cavity is directly below the first dielectric cap and is laterally between the first conductive wire and the second conductive wire. The first cavity is defined by one or more surfaces of the first dielectric cap.

公开(公告)号：US11798840B2

公开(公告)日：2023-10-24

申请号：US17337753

申请日：2021-06-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Hao Liao ,  Hsi-Wen Tien ,  Chih Wei Lu ,  Yu-Teng Dai ,  Hsin-Chieh Yao ,  Chung-Ju Lee

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L21/76831 ,  H01L21/76832 ,  H01L23/5226

摘要： Some embodiments of the present disclosure relate to a semiconductor structure including a first conductive wire disposed over a substrate. A dielectric liner is arranged along sidewalls and an upper surface of the first conductive wire and is laterally surrounded by a first dielectric layer. The dielectric liner and the first dielectric layer are different materials. A conductive via is disposed within a second dielectric layer over the first conductive wire. The conductive via has a first lower surface disposed over the first dielectric layer and a second lower surface below the first lower surface and over the first conductive wire.

公开(公告)号：US20220415704A1

公开(公告)日：2022-12-29

申请号：US17356959

申请日：2021-06-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsi-Wen Tien ,  Wei-Hao Liao ,  Yu-Teng Dai ,  Hsin-Chieh Yao ,  Chih-Wei Lu ,  Chung-Ju Lee ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L21/033 ,  H01L23/522 ,  H01L23/528

摘要： A method of forming a semiconductor device structure is provided. The method includes forming a masking structure with first openings over a semiconductor substrate and correspondingly forming metal layers in the first openings. The method also includes recessing the masking structure to form second openings between the metal layers and forming a sacrificial layer surrounded by a first liner in each of the second openings. In addition, after forming a second liner over the sacrificial layer in each of the second openings, the method includes removing the sacrificial layer in each of the second openings to form a plurality of air gaps therefrom.

公开(公告)号：US20220230963A1

公开(公告)日：2022-07-21

申请号：US17714428

申请日：2022-04-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Hao Liao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Yu-Teng Dai

IPC分类号： H01L23/532 ,  H01L23/522 ,  H01L21/768

摘要： The present disclosure relates to an integrated chip comprising a pair of first metal lines over a substrate. A first interlayer dielectric (ILD) layer is laterally between the pair of first metal lines. The first ILD layer comprises a first dielectric material. A pair of spacers are on opposite sides of the first ILD layer and are laterally separated from the first ILD layer by a pair of cavities. The pair of spacers comprise a second dielectric material. Further, the pair of cavities are defined by opposing sidewalls of the first ILD layer and sidewalls of the pair of spacers that face the first ILD layer.