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公开(公告)号：US09355964B2
公开(公告)日：2016-05-31
申请号：US14203242
申请日：2014-03-10
发明人： Cheng-Hsien Chou , Sheng-Chau Chen , Chun-Wei Chang , Kai-Chun Hsu , Chih-Yu Lai , Wei-Cheng Hsu , Hsiao-Hui Tseng , Shih Pei Chou , Shyh-Fann Ting , Tzu-Hsuan Hsu , Ching-Chun Wang , Yeur-Luen Tu , Dun-Nian Yaung
IPC分类号： H01L21/78 , H01L23/544 , H01L21/762
CPC分类号： H01L23/544 , H01L21/02164 , H01L21/02233 , H01L21/308 , H01L21/7621 , H01L21/76224 , H01L27/1463 , H01L27/14632 , H01L27/14687 , H01L29/0649 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.
摘要翻译： 介绍了一种制造非STI CMOS图像传感器对准标记的方法。 在一些实施例中，可以在晶片上同时形成零层对准标记和活性物质对准标记。 可以将晶片的衬底图案化以在衬底中形成一个或多个凹槽。 可以使用例如场氧化方法和/或合适的沉积方法用电介质材料填充凹部。 通过上述过程形成的结构可以对应于零层对准标记的元素和/或对应于有源区对准标记的元件。
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公开(公告)号：US10074612B2
公开(公告)日：2018-09-11
申请号：US15477971
申请日：2017-04-03
发明人： Cheng-Hsien Chou , Sheng-Chau Chen , Chun-Wei Chang , Kai-Chun Hsu , Chih-Yu Lai , Wei-Cheng Hsu , Hsiao-Hui Tseng , Shih Pei Chou , Shyh-Fann Ting , Tzu-Hsuan Hsu , Ching-Chun Wang , Yeur-Luen Tu , Dun-Nian Yaung
IPC分类号： H01L21/78 , H01L23/544 , H01L21/762 , H01L29/06 , H01L21/308 , H01L21/02 , H01L27/146
CPC分类号： H01L23/544 , H01L21/02164 , H01L21/02233 , H01L21/308 , H01L21/7621 , H01L21/76224 , H01L27/1463 , H01L27/14632 , H01L27/14687 , H01L29/0649 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.
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公开(公告)号：US20170207176A1
公开(公告)日：2017-07-20
申请号：US15477971
申请日：2017-04-03
发明人： Cheng-Hsien Chou , Sheng-Chau Chen , Chun-Wei Chang , Kai-Chun Hsu , Chih-Yu Lai , Wei-Cheng Hsu , Hsiao-Hui Tseng , Shih Pei Chou , Shyh-Fann Ting , Tzu-Hsuan Hsu , Ching-Chun Wang , Yeur-Luen Tu , Dun-Nian Yaung
IPC分类号： H01L23/544 , H01L27/146 , H01L21/308 , H01L21/02 , H01L21/762 , H01L29/06
CPC分类号： H01L23/544 , H01L21/02164 , H01L21/02233 , H01L21/308 , H01L21/7621 , H01L21/76224 , H01L27/1463 , H01L27/14632 , H01L27/14687 , H01L29/0649 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.
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公开(公告)号：US20160276285A1
公开(公告)日：2016-09-22
申请号：US15165834
申请日：2016-05-26
发明人： Cheng-Hsien Chou , Sheng-Chau Chen , Chun-Wei Chang , Kai-Chun Hsu , Chih-Yu Lai , Wei-Cheng Hsu , Hsiao-Hui Tseng , Shih Pei Chou , Shyh-Fann Ting , Tzu-Hsuan Hsu , Ching-Chun Wang , Yeur-Luen Tu , Dun-Nian Yaung
IPC分类号： H01L23/544 , H01L21/762
CPC分类号： H01L23/544 , H01L21/02164 , H01L21/02233 , H01L21/308 , H01L21/7621 , H01L21/76224 , H01L27/1463 , H01L27/14632 , H01L27/14687 , H01L29/0649 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.
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公开(公告)号：US20230378221A1
公开(公告)日：2023-11-23
申请号：US17866846
申请日：2022-07-18
发明人： Cheng-Ying Ho , Wen-De Wang , Kai-Chun Hsu , Sung-En Lin , Yuh-Ruey Huang , Jen-Cheng Liu
IPC分类号： H01L27/146
CPC分类号： H01L27/14636 , H01L27/1463 , H01L27/14614 , H01L27/14685 , H01L27/14689
摘要： The present disclosure relates to an image sensor integrated chip (IC). The image sensor IC includes one or more interconnects arranged within an inter-level dielectric (ILD) structure on a first side of a substrate. An image sensing element is arranged within the substrate. Sidewalls of the substrate form one or more trenches extending from a second side of the substrate to within the substrate on opposing sides of the image sensing element. A dielectric structure is arranged on the sidewalls of the substrate that form the one or more trenches. A conductive core is arranged within the one or more trenches and is laterally separated from the substrate by the dielectric structure. The conductive core is electrically coupled to the one or more interconnects.
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公开(公告)号：US20220254828A1
公开(公告)日：2022-08-11
申请号：US17729258
申请日：2022-04-26
IPC分类号： H01L27/146 , H01L23/00
摘要： The present disclosure relates to a semiconductor structure. The semiconductor structure includes a dielectric layer having a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The dielectric layer defines a recess in the first dielectric surface, and the recess includes a sidewall of the dielectric layer. A first conductive layer contacts a bottom surface of the dielectric layer. The sidewall of the dielectric layer is directly over the first conductive layer. A second conductive layer contacts the first conductive layer and the dielectric layer. The second conductive layer vertically extends from the first conductive layer to above the dielectric layer. A third conductive layer contacts the second conductive layer. The third conductive layer is laterally separated from a sidewall of the second conductive layer that faces the third conductive layer by a non-zero distance.
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公开(公告)号：US11996433B2
公开(公告)日：2024-05-28
申请号：US17729258
申请日：2022-04-26
IPC分类号： H01L27/146 , H01L23/00
CPC分类号： H01L27/14636 , H01L24/05 , H01L27/14603 , H01L27/1462 , H01L27/14645 , H01L27/14685 , H01L27/14621 , H01L27/14627 , H01L2224/0401 , H01L2224/05017 , H01L2224/05024 , H01L2224/05026 , H01L2224/05566 , H01L2224/05573 , H01L2224/05582 , H01L2224/05686 , H01L2924/14 , H01L2924/14 , H01L2924/00012
摘要： The present disclosure relates to a semiconductor structure. The semiconductor structure includes a dielectric layer having a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The dielectric layer defines a recess in the first dielectric surface, and the recess includes a sidewall of the dielectric layer. A first conductive layer contacts a bottom surface of the dielectric layer. The sidewall of the dielectric layer is directly over the first conductive layer. A second conductive layer contacts the first conductive layer and the dielectric layer. The second conductive layer vertically extends from the first conductive layer to above the dielectric layer. A third conductive layer contacts the second conductive layer. The third conductive layer is laterally separated from a sidewall of the second conductive layer that faces the third conductive layer by a non-zero distance.
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公开(公告)号：US20230326951A1
公开(公告)日：2023-10-12
申请号：US17861708
申请日：2022-07-11
发明人： Cheng-Ying Ho , Wen-De Wang , Keng-Yu Chou , Kai-Chun Hsu , Tzu-Hsuan Hsu , Jen-Cheng Liu
IPC分类号： H01L27/146 , H01L21/762
CPC分类号： H01L27/1464 , H01L21/76224 , H01L27/14685 , H01L27/14636
摘要： Various embodiments of the present disclosure are directed towards an image sensor having a photodetector disposed within a semiconductor substrate. A dielectric structure is disposed on a first side of the semiconductor substrate. An isolation structure extends from the dielectric structure into the first side of the semiconductor substrate. The isolation structure laterally wraps around the photodetector and comprises an upper portion disposed above the first side of the semiconductor substrate and directly contacting sidewalls of the dielectric structure. The isolation structure comprises a first material different from a second material of the dielectric structure.
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公开(公告)号：US09627326B2
公开(公告)日：2017-04-18
申请号：US15165834
申请日：2016-05-26
发明人： Cheng-Hsien Chou , Sheng-Chau Chen , Chun-Wei Chang , Kai-Chun Hsu , Chih-Yu Lai , Wei-Cheng Hsu , Hsiao-Hui Tseng , Shih Pei Chou , Shyh-Fann Ting , Tzu-Hsuan Hsu , Ching-Chun Wang , Yeur-Luen Tu , Dun-Nian Yaung
IPC分类号： H01L21/762 , H01L23/544
CPC分类号： H01L23/544 , H01L21/02164 , H01L21/02233 , H01L21/308 , H01L21/7621 , H01L21/76224 , H01L27/1463 , H01L27/14632 , H01L27/14687 , H01L29/0649 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.
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公开(公告)号：US20150255400A1
公开(公告)日：2015-09-10
申请号：US14203242
申请日：2014-03-10
发明人： Cheng-Hsien Chou , Sheng-Chau Chen , Chun-Wei Chang , Kai-Chun Hsu , Chih-Yu Lai , Wei-Cheng Hsu , Hsiao-Hui Tseng , Shih Pei Chou , Shyh-Fann Ting , Tzu-Hsuan Hsu , Ching-Chun Wang , Yeur-Luen Tu , Dun-Nian Yaung
IPC分类号： H01L23/544 , H01L21/762
CPC分类号： H01L23/544 , H01L21/02164 , H01L21/02233 , H01L21/308 , H01L21/7621 , H01L21/76224 , H01L27/1463 , H01L27/14632 , H01L27/14687 , H01L29/0649 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.
摘要翻译： 介绍了一种制造非STI CMOS图像传感器对准标记的方法。 在一些实施例中，可以在晶片上同时形成零层对准标记和活性物质对准标记。 可以将晶片的衬底图案化以在衬底中形成一个或多个凹槽。 可以使用例如场氧化方法和/或合适的沉积方法用电介质材料填充凹部。 通过上述过程形成的结构可以对应于零层对准标记的元素和/或对应于有源区对准标记的元件。
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