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1.发明申请公开(公告)号：US20160005645A1
公开(公告)日：2016-01-07
申请号：US14857954
申请日：2015-09-18
发明人： Kuo-Chin CHANG , Yuh Chern SHIEH
IPC分类号： H01L21/768 , H01L23/00
CPC分类号： H01L23/528 , H01L21/76802 , H01L21/76837 , H01L23/3171 , H01L23/5283 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/0346 , H01L2224/03472 , H01L2224/0391 , H01L2224/0401 , H01L2224/05012 , H01L2224/05016 , H01L2224/05026 , H01L2224/05147 , H01L2224/05568 , H01L2224/05571 , H01L2224/05647 , H01L2224/1145 , H01L2224/1146 , H01L2224/1147 , H01L2224/13006 , H01L2224/13023 , H01L2224/13147 , H01L2924/00014 , H01L2924/01012 , H01L2924/01327 , H01L2924/1305 , H01L2924/1306 , H01L2924/014 , H01L2924/01047 , H01L2924/01024 , H01L2924/01028 , H01L2924/0105 , H01L2924/01079 , H01L2924/00012 , H01L2924/00 , H01L2224/05552
摘要： A method for fabricating a semiconductor device includes forming a first photo-sensitive layer over a contact pad, wherein the contact pad is on a substrate. The method further includes patterning the first photo-sensitive layer to form a first opening over a portion of the contact pad. The method further includes plating a conductive via in the first opening; and removing the first photo-sensitive layer. The method further includes forming a passivation layer over the substrate, contact pad, and conductive via, and exposing the conductive via by grinding the passivation layer. The method further includes forming a second photo-sensitive layer over the conductive via and passivation layer. The method further includes patterning the second photo-sensitive layer to form a second opening larger than and completely exposing the conductive via. The method further includes plating a conductive pillar in the second opening; and removing the second photo-sensitive layer.
摘要翻译： 一种制造半导体器件的方法包括在接触焊盘上形成第一感光层，其中接触焊盘位于衬底上。 该方法还包括图案化第一感光层以在接触垫的一部分上形成第一开口。 该方法还包括在第一开口中镀覆导电通孔; 并移除第一光敏层。 该方法还包括在衬底，接触焊盘和导电通孔上形成钝化层，以及通过研磨钝化层来暴露导电通孔。 该方法还包括在导电通孔和钝化层上形成第二光敏层。 该方法还包括图案化第二感光层以形成大于并完全暴露导电通孔的第二开口。 该方法还包括在第二开口中电镀导电柱; 并移除第二光敏层。
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公开(公告)号：US20240120277A1
公开(公告)日：2024-04-11
申请号：US18543110
申请日：2023-12-18
发明人： Hong-Seng SHUE , Sheng-Han TSAI , Kuo-Chin CHANG , Mirng-Ji LII , Kuo-Ching HSU
IPC分类号： H01L23/528 , H01L23/00 , H01L23/522
CPC分类号： H01L23/5283 , H01L23/5226 , H01L24/08 , H01L24/09 , H01L24/11 , H01L24/16 , H01L24/17 , H01L2224/02235 , H01L2224/0224 , H01L2224/02245 , H01L2224/0225 , H01L2224/02255 , H01L2224/023 , H01L2224/0231 , H01L2224/0233 , H01L2224/02373 , H01L2224/02381 , H01L2224/0401 , H01L2224/0805 , H01L2224/08052 , H01L2224/081 , H01L2224/08113 , H01L2224/16104
摘要： A chip structure is provided. The chip structure includes a substrate, a redistribution layer over the substrate, a bonding pad over the redistribution layer, a shielding pad over the redistribution layer and surrounding the bonding pad, an insulating layer over the redistribution layer and the shielding pad, and a bump over the bonding pad and the insulating layer. The insulating layer includes a first part and a second part surrounded by the first part, the first part has first thickness, the second part has a second thickness, and the first thickness and the second thickness are different.
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公开(公告)号：US20220384286A1
公开(公告)日：2022-12-01
申请号：US17818437
申请日：2022-08-09
发明人： Shin CHI , Chien Hao HSU , Kuo-Chin CHANG , Cheng-Nan LIN , Mirng-Ji LII
IPC分类号： H01L23/31 , H01L23/367 , H01L21/56 , H01L21/48 , H01L23/00
摘要： A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a first heat conductive layer between the heat-spreading wall structure and the chip. The chip package structure includes a second heat conductive layer over the chip and surrounded by the first heat conductive layer. The chip package structure includes a heat-spreading lid over the substrate and covering the heat-spreading wall structure, the first heat conductive layer, the second heat conductive layer, and the chip. The heat-spreading lid is bonded to the substrate, the heat-spreading wall structure, the first heat conductive layer, and the second heat conductive layer.
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公开(公告)号：US20170062329A1
公开(公告)日：2017-03-02
申请号：US15351697
申请日：2016-11-15
发明人： Kuo-Chin CHANG , Yuh Chern SHIEH
IPC分类号： H01L23/528 , H01L23/00 , H01L21/768
CPC分类号： H01L23/528 , H01L21/76802 , H01L21/76837 , H01L23/3171 , H01L23/5283 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/0346 , H01L2224/03472 , H01L2224/0391 , H01L2224/0401 , H01L2224/05012 , H01L2224/05016 , H01L2224/05026 , H01L2224/05147 , H01L2224/05568 , H01L2224/05571 , H01L2224/05647 , H01L2224/1145 , H01L2224/1146 , H01L2224/1147 , H01L2224/13006 , H01L2224/13023 , H01L2224/13147 , H01L2924/00014 , H01L2924/01012 , H01L2924/01327 , H01L2924/1305 , H01L2924/1306 , H01L2924/014 , H01L2924/01047 , H01L2924/01024 , H01L2924/01028 , H01L2924/0105 , H01L2924/01079 , H01L2924/00012 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor device includes a substrate and a contact pad over the substrate. The semiconductor device further includes a conductive via electrically connected to the contact pad. The conductive via includes a conductive via layer having a first thickness, and a first conductive layer, wherein the first conductive layer is between the contact pad and the conductive via layer. The semiconductor device further includes a conductive pillar electrically connected to the conductive via. The conductive pillar includes a conductive pillar layer having a second thickness, and a second conductive layer having outer edges substantially aligned with outer edges of the conductive pillar layer, wherein the second conductive layer is between the conductive via layer and the conductive pillar layer. A ratio of the first thickness to the second thickness ranges from about 0.33 to about 0.55.
摘要翻译： 半导体器件包括衬底和衬底上的接触焊盘。 半导体器件还包括电连接到接触焊盘的导电通孔。 导电通孔包括具有第一厚度的导电通孔层和第一导电层，其中第一导电层位于接触焊盘和导电通孔层之间。 半导体器件还包括与导电通孔电连接的导电柱。 导电柱包括具有第二厚度的导电柱层和具有与导电柱层的外边缘基本对准的外边缘的第二导电层，其中第二导电层在导电通孔层和导电柱层之间。 第一厚度与第二厚度的比率为约0.33至约0.55。
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