公开(公告)号：US20150318225A1

公开(公告)日：2015-11-05

申请号：US14798857

申请日：2015-07-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Ying-Ju CHEN ,  Hsien-Wei CHEN ,  Hao-Yi TSAI ,  Mirng-Ji LII

IPC分类号： H01L21/66 ,  H01L23/522 ,  H01L23/00 ,  H01L23/532 ,  H01L29/06 ,  H01L23/538 ,  H01L23/50 ,  H01L23/528

CPC分类号： H01L22/34 ,  H01L22/32 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/5383 ,  H01L24/05 ,  H01L29/0649 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/14 ,  H01L2924/00

摘要： A wafer including a substrate having a plurality of integrated circuits formed above the substrate, and at least one scribe line between two of the integrated circuits. The wafer further includes a plurality of dielectric layers formed in the at least one scribe line having a process control monitor (PCM) pad structure formed therein, the PCM pad structure having: a plurality of metal pads interconnected by a plurality of conductive vias. The PCM pad further includes a plurality of contact bars in contact with a bottom-most metal pad, the contact bars extending substantially vertically from the bottom-most metal pad into the substrate. Additionally, the PCM pad includes an isolation structure substantially surrounding the plurality of contact bars to isolate the PCM pad structure.

摘要翻译： 包括具有形成在基板上方的多个集成电路的基板和在两个集成电路之间的至少一个划线的晶片。 所述晶片还包括形成在所述至少一个划线中的多个电介质层，其具有形成在其中的过程控制监视器（PCM）焊盘结构，所述PCM焊盘结构具有：通过多个导电通孔互连的多个金属焊盘。 PCM垫还包括与最底部金属垫接触的多个接触棒，接触杆从最底部的金属垫基本垂直地延伸到衬底中。 此外，PCM垫包括基本上围绕多个接触棒的隔离结构，以隔离PCM垫结构。

公开(公告)号：US20230062138A1

公开(公告)日：2023-03-02

申请号：US17460868

申请日：2021-08-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Hao TSAI ,  Wei-Hung LIN ,  Ming-Da CHENG ,  Mirng-Ji LII

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L25/18 ,  H01L21/48

摘要： A semiconductor package structure includes first via structures formed through a core substrate. The structure also includes an interposer embedded in the core substrate between the first via structures. The interposer includes second via structures formed through an interposer substrate. The structure also includes a first redistribution layer structure formed over the core substrate. The structure also includes a second redistribution layer structure formed under the core substrate. The structure also includes a first encapsulating layer formed between a sidewall of the interposer and a sidewall of the core substrate.

公开(公告)号：US20230060982A1

公开(公告)日：2023-03-02

申请号：US17460709

申请日：2021-08-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ting-Li YANG ,  Wen-Hsiung LU ,  Lung-Kai MAO ,  Fu-Wei LIU ,  Mirng-Ji LII

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L21/306

摘要： A method for forming a semiconductor device structure is provided. The method includes providing a chip structure including a substrate and a wiring structure over a first surface of the substrate. The method includes removing a first portion of the wiring structure adjacent to the hole to widen a second portion of the hole in the wiring structure. The second portion has a first width increasing in a first direction away from the substrate. The method includes forming a first seed layer over the wiring structure and in the hole. The method includes thinning the substrate from a second surface of the substrate until the first seed layer in the hole is exposed. The method includes forming a second seed layer over the second surface of the substrate and the first seed layer in the hole.

公开(公告)号：US20230021764A1

公开(公告)日：2023-01-26

申请号：US17936959

申请日：2022-09-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Hao TSAI ,  Ming-Da CHENG ,  Mirng-Ji LII

IPC分类号： H01L25/065 ,  H01L23/538 ,  H01L25/00 ,  H01L23/31 ,  H01L23/42 ,  H01L21/52 ,  H01L21/56

摘要： A method for forming a package structure is provided. The method includes etching a top surface of a substrate to form a cavity. The substrate includes thermal vias directly under a bottom surface of the cavity. The method also includes forming at least one first electronic device in the cavity of the substrate. The first electronic device is thermally coupled to the thermal vias. The method further includes forming an encapsulating material in the cavity, so that the encapsulating material extends along sidewalls of the first electronic device and covers a surface of the first electronic device opposite the bottom surface of the cavity. In Addition, the method includes forming an insulating layer having an RDL structure over the encapsulating material. The RDL structure is electrically connected to the first electronic device.

公开(公告)号：US20210384152A1

公开(公告)日：2021-12-09

申请号：US17409138

申请日：2021-08-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-En YEN ,  Chin-Wei KANG ,  Kai-Jun ZHAN ,  Wen-Hsiung LU ,  Cheng-Jen LIN ,  Ming-Da CHENG ,  Mirng-Ji LII

IPC分类号： H01L23/00

摘要： A semiconductor device is provided. The semiconductor device includes a substrate having a surface. The semiconductor device includes a conductive pad over a portion of the surface. The conductive pad has a curved top surface, and a width of the conductive pad increases toward the substrate. The semiconductor device includes a device over the conductive pad. The semiconductor device includes a solder layer between the device and the conductive pad. The solder layer covers the curved top surface of the conductive pad, and the conductive pad extends into the solder layer.

公开(公告)号：US20210280477A1

公开(公告)日：2021-09-09

申请号：US17328801

申请日：2021-05-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Mill-Jer WANG ,  Tang-Jung CHIU ,  Chi-Chang LAI ,  Chia-Heng TSAI ,  Mirng-Ji LII ,  Weii LIAO

IPC分类号： H01L21/66 ,  H01L23/552 ,  H01L27/01

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first magnetic element and a second magnetic element over the semiconductor substrate. The semiconductor device structure also includes a first conductive line extending exceeding an edge of the first magnetic element. The semiconductor device structure further includes a second conductive line extending exceeding an edge of the second magnetic element. The second conductive line is electrically connected to the first conductive line.

公开(公告)号：US20220384286A1

公开(公告)日：2022-12-01

申请号：US17818437

申请日：2022-08-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shin CHI ,  Chien Hao HSU ,  Kuo-Chin CHANG ,  Cheng-Nan LIN ,  Mirng-Ji LII

IPC分类号： H01L23/31 ,  H01L23/367 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00

摘要： A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a first heat conductive layer between the heat-spreading wall structure and the chip. The chip package structure includes a second heat conductive layer over the chip and surrounded by the first heat conductive layer. The chip package structure includes a heat-spreading lid over the substrate and covering the heat-spreading wall structure, the first heat conductive layer, the second heat conductive layer, and the chip. The heat-spreading lid is bonded to the substrate, the heat-spreading wall structure, the first heat conductive layer, and the second heat conductive layer.

公开(公告)号：US20160043051A1

公开(公告)日：2016-02-11

申请号：US14455615

申请日：2014-08-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Yen-Liang LIN ,  Mirng-Ji LII ,  Tin-Hao KUO ,  Chen-Shien CHEN ,  Yu-Feng CHEN ,  Sheng-Yu WU

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/498 ,  H01L23/522

CPC分类号： H01L24/17 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/1705 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/3841 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/014

摘要： The present disclosure provides a semiconductor package, including a semiconductor die and a substrate having a first surface electrically coupled to the semiconductor die and a second surface opposing to the first surface. The first surface includes a core region having a plurality of landing pads and a periphery region surrounding the core region and having a plurality of landing traces. A pitch of the landing pads is from about 55 μm to about 280 μm. The semiconductor die includes a third surface facing the first surface of the substrate and a fourth surface opposing to the third surface. The third surface includes a plurality of elongated bump positioned correspondingly to the landing pads and the landing traces of the substrate, and the elongated bump includes a long axis and a short axis perpendicular to the long axis on a cross section thereof.

摘要翻译： 本公开提供了半导体封装，其包括半导体管芯和具有电耦合到半导体管芯的第一表面的衬底和与第一表面相对的第二表面。 第一表面包括具有多个着陆焊盘的芯区域和围绕芯区域并具有多个着陆迹线的外围区域。 着陆垫的间距为约55μm至约280μm。 半导体管芯包括面向衬底的第一表面的第三表面和与第三表面相对的第四表面。 第三表面包括对应于基板的着陆焊盘和着陆迹线定位的多个细长凸块，并且细长凸块包括在其横截面上与长轴垂直的长轴和短轴。

公开(公告)号：US20140045326A1

公开(公告)日：2014-02-13

申请号：US14058466

申请日：2013-10-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shih-Wei LIANG ,  Hsien-Wei CHEN ,  Ying-Ju CHEN ,  Tsung-Yuan YU ,  Mirng-Ji LII

IPC分类号： H01L23/00 ,  H01L21/768

CPC分类号： H01L24/11 ,  H01L21/76841 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/525 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05571 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2924/00

摘要： A method of making a semiconductor device includes forming a passivation layer overlying a semiconductor substrate, the semiconductor substrate having a first region and a second region, wherein the first region is a conductive pad and the second region is adjacent to the first region. The method further includes forming a first protective layer overlying the passivation layer and forming an interconnect layer overlying the first protective layer. The method further includes forming a plurality of slots in the second region and forming a second protective layer overlying the interconnect layer, wherein the second protective layer fills each slot of the plurality of slots. The method further includes exposing a portion of the interconnect layer through the second protective layer; forming a barrier layer on the exposed portion of the interconnect layer; and forming a solder bump on the barrier layer.

摘要翻译： 制造半导体器件的方法包括形成覆盖半导体衬底的钝化层，所述半导体衬底具有第一区域和第二区域，其中所述第一区域是导电焊盘，所述第二区域与所述第一区域相邻。 该方法还包括形成覆盖钝化层的第一保护层，并形成覆盖第一保护层的互连层。 所述方法还包括在所述第二区域中形成多个狭槽并形成覆盖所述互连层的第二保护层，其中所述第二保护层填充所述多个槽的每个槽。 所述方法还包括将所述互连层的一部分暴露于所述第二保护层; 在所述互连层的暴露部分上形成阻挡层; 并在阻挡层上形成焊料凸块。

公开(公告)号：US20190074255A1

公开(公告)日：2019-03-07

申请号：US16181130

申请日：2018-11-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsien-Wei CHEN ,  Hao-Yi TSAI ,  Mirng-Ji LII ,  Chen-Hua YU

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/525

CPC分类号： H01L23/562 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/525 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate, a passivation layer overlying the semiconductor substrate, and an interconnect structure overlying the passivation layer. The interconnect structure includes a landing pad region and a dummy region electrically separated from each other. A protective layer is formed on the interconnect structure and has a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region. A metal layer is formed on the exposed portion of landing pad region and the exposed portion of the dummy region. A bump is formed on the metal layer overlying the landing pad region.