专利检索 cpc:"H01L2224/0224" 第 1 页

1.

发明授权
Method for bonding substrates 有权

公开(公告)号：US09859246B2

公开(公告)日：2018-01-02

申请号：US14917318

申请日：2014-12-18

申请人： EV GROUP E. THALLNER GMBH

发明人： Andreas Fehkuhrer

IPC分类号： H01L21/00 , H01L23/00 , B32B37/00 , H01L21/18 , H01L21/304 , H01L21/67 , H01L21/683 , H01L25/065 , H01L25/00 , H01L23/544 , B32B38/18

CPC分类号： H01L24/80 , B32B37/0046 , B32B38/1841 , B32B38/1858 , B32B2309/105 , B32B2457/14 , H01L21/187 , H01L21/304 , H01L21/67092 , H01L21/6831 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L23/544 , H01L24/08 , H01L24/74 , H01L24/75 , H01L24/94 , H01L24/95 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/68363 , H01L2221/68368 , H01L2221/68381 , H01L2223/54426 , H01L2223/54453 , H01L2224/0224 , H01L2224/0381 , H01L2224/0382 , H01L2224/03831 , H01L2224/0384 , H01L2224/08121 , H01L2224/08145 , H01L2224/74 , H01L2224/75251 , H01L2224/75272 , H01L2224/75701 , H01L2224/75702 , H01L2224/75704 , H01L2224/75705 , H01L2224/75724 , H01L2224/75725 , H01L2224/75734 , H01L2224/75735 , H01L2224/75744 , H01L2224/75745 , H01L2224/7598 , H01L2224/80 , H01L2224/80003 , H01L2224/80006 , H01L2224/8001 , H01L2224/80011 , H01L2224/8002 , H01L2224/80047 , H01L2224/80051 , H01L2224/80093 , H01L2224/80099 , H01L2224/8013 , H01L2224/80132 , H01L2224/80201 , H01L2224/80203 , H01L2224/80209 , H01L2224/80213 , H01L2224/80801 , H01L2224/80894 , H01L2224/80907 , H01L2224/92 , H01L2224/94 , H01L2224/95 , H01L2224/97 , H01L2225/06565 , H01L2924/00014 , H01L2924/00012 , H01L2221/68304

摘要： A method for bonding a first substrate with a second substrate, characterized in that the first substrate and/or the second substrate is/are thinned before the bonding.

2.

发明申请
Method for Aligning Micro-Electronic Components 有权

公开(公告)号：US20170186733A1

公开(公告)日：2017-06-29

申请号：US15457744

申请日：2017-03-13

申请人： IMEC VZW , Katholieke Universiteit Leuven, KU LEUVEN R&D

发明人： Vikas Dubey , Ingrid De Wolf , Eric Beyne

IPC分类号： H01L25/065 , H01L25/00 , H01L23/31 , H01L23/00 , H01L23/528

CPC分类号： H01L25/0657 , H01L23/3157 , H01L23/3192 , H01L23/528 , H01L24/02 , H01L24/05 , H01L24/08 , H01L24/09 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/33 , H01L24/80 , H01L24/81 , H01L24/83 , H01L25/50 , H01L2224/0213 , H01L2224/0214 , H01L2224/02145 , H01L2224/0217 , H01L2224/02175 , H01L2224/0218 , H01L2224/02185 , H01L2224/0224 , H01L2224/0225 , H01L2224/02255 , H01L2224/0401 , H01L2224/05647 , H01L2224/08145 , H01L2224/08225 , H01L2224/0903 , H01L2224/10135 , H01L2224/10145 , H01L2224/10165 , H01L2224/10175 , H01L2224/13147 , H01L2224/16145 , H01L2224/16147 , H01L2224/16148 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/1703 , H01L2224/80004 , H01L2224/80007 , H01L2224/80121 , H01L2224/8013 , H01L2224/80132 , H01L2224/80143 , H01L2224/80203 , H01L2224/80894 , H01L2224/80907 , H01L2224/81002 , H01L2224/81007 , H01L2224/81121 , H01L2224/8113 , H01L2224/81132 , H01L2224/81141 , H01L2224/81143 , H01L2224/81191 , H01L2224/81193 , H01L2224/81815 , H01L2224/81894 , H01L2224/81907 , H01L2224/83143 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06593 , H01L2924/14 , H01L2924/3511 , H01L2924/00012 , H01L2924/00014

摘要： Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves the alignment obtained through capillary force and maintains the alignment during evaporation of the liquid.

3.

发明授权
Semiconductor package 有权
标题翻译：半导体封装

公开(公告)号：US09418944B2

公开(公告)日：2016-08-16

申请号：US14739829

申请日：2015-06-15

申请人： J-DEVICES CORPORATION

发明人： Kiyoaki Hashimoto , Yasuyuki Takehara

IPC分类号： H01L23/00 , H01L23/544 , H01L23/36 , H01L23/373 , H01L21/48 , H01L23/31 , H01L21/56 , H01L23/498

CPC分类号： H01L23/562 , H01L21/4857 , H01L21/4882 , H01L21/561 , H01L21/565 , H01L21/568 , H01L23/3128 , H01L23/36 , H01L23/3735 , H01L23/49816 , H01L23/5389 , H01L23/544 , H01L24/02 , H01L24/13 , H01L24/19 , H01L24/97 , H01L25/0655 , H01L2223/54426 , H01L2223/54486 , H01L2224/0224 , H01L2224/02315 , H01L2224/02331 , H01L2224/02373 , H01L2224/02379 , H01L2224/0239 , H01L2224/04105 , H01L2224/12105 , H01L2224/13024 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2924/01029 , H01L2924/3511 , H01L2224/83 , H01L2224/82

摘要： A semiconductor package includes a support substrate; a stress relaxation layer provided on a main surface of the support substrate; a semiconductor device located on the stress relaxation layer; an encapsulation material covering the semiconductor device, the encapsulation material being formed of an insulating material different from that of the stress relaxation layer; a line running through the encapsulation material and electrically connected to the semiconductor device; and an external terminal electrically connected to the line. Where the support substrate has an elastic modulus of A, the stress relaxation layer has an elastic modulus of B, and the encapsulation material has an elastic modulus of C under a same temperature condition, the relationship of A>C>B or C>A>B is obtained.

摘要翻译： 半导体封装包括支撑衬底; 设置在所述支撑基板的主表面上的应力松弛层; 位于应力松弛层上的半导体器件; 覆盖半导体器件的封装材料，封装材料由与应力松弛层不同的绝缘材料形成; 穿过封装材料并电连接到半导体器件的线; 以及与该线路电连接的外部端子。在支撑基板具有A的弹性模量的情况下，应力松弛层的弹性模量为B，封装材料在相同的温度条件下具有C的弹性模量，A> C> B或C> A的关系 > B。

4.

发明授权
Method of measuring photoresist and bump misalignment 有权
标题翻译：测量光刻胶和凸块未对准的方法

公开(公告)号：US06636313B2

公开(公告)日：2003-10-21

申请号：US10045413

申请日：2002-01-12

申请人： Yen-Ming Chen , Chia-Fu Lin , Kai-Ming Ching , Chao-Yuan Su , Hsin-Hui Lee , Li-Chih Chen

发明人： Yen-Ming Chen , Chia-Fu Lin , Kai-Ming Ching , Chao-Yuan Su , Hsin-Hui Lee , Li-Chih Chen

IPC分类号： G01B1100

CPC分类号： G03F7/70633 , G01B11/272 , H01L24/11 , H01L2224/0224 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/0508 , H01L2224/05093 , H01L2224/05572 , H01L2924/14 , H01L2924/00

摘要： A method including the acts of providing a semiconductor device having a plurality of misalignment ruler markers formed therein for measuring removable layer opening misalignment in the X and Y directions, a bond pad and the passivation layer with an opening therein down to the bond pad. A removable layer is formed over the semiconductor device and includes an opening therein down to the bond pad. Preferably this action includes depositing, patterning and developing a dry photoresist film layer over the semiconductor device with an opening therein down to the bond pad. The next act includes measuring the misalignment of the opening in the passivation layer by counting the number of misalignment ruler markers visibly exposed by the opening in the X-direction and also the Y-direction.

摘要翻译： 一种方法，包括提供半导体器件的动作，所述半导体器件具有形成在其中的多个不对准标尺标记，用于测量在X和Y方向上的可移除层开口未对准，接合焊盘和钝化层，其中开口向下到接合焊盘。可移除层形成在半导体器件上方并且包括其中向下到达接合焊盘的开口。优选地，该动作包括在半导体器件上沉积，图案化和显影干的光致抗蚀剂膜层，其中开口向下到接合焊盘。下一个动作包括通过计数由X方向和Y方向上的开口可见地露出的未对准标尺标记的数量来测量钝化层中的开口的未对准。

5.

发明公开
DRIVING SUBSTRATE, MICRO LED TRANSFER DEVICE AND MICRO LED TRANSFER METHOD 审中-公开

公开(公告)号：US20240153908A1

公开(公告)日：2024-05-09

申请号：US18204965

申请日：2023-06-02

申请人： HKC CORPORATION LIMITED

发明人： Yang PU , Haoxuan Zheng

IPC分类号： H01L23/00 , H01L25/16 , H01L33/38 , H01L33/62

CPC分类号： H01L24/81 , H01L24/02 , H01L24/05 , H01L24/10 , H01L24/13 , H01L24/16 , H01L25/167 , H01L33/38 , H01L33/62 , H01L2224/0217 , H01L2224/0224 , H01L2224/05555 , H01L2224/05573 , H01L2224/05609 , H01L2224/05611 , H01L2224/10135 , H01L2224/10165 , H01L2224/13016 , H01L2224/16145 , H01L2224/81002 , H01L2224/81005 , H01L2224/81139 , H01L2224/8114 , H01L2224/81141 , H01L2224/818 , H01L2924/12041 , H01L2924/13069 , H01L2924/13091

摘要： A driving substrate, a micro LED transfer device and a micro LED transfer method are provided. A side surface of the driving substrate is arranged with a binding metal layer, a positioning layer is arranged around the binding metal layer, and a width of the positioning layer at a position away from the driving substrate is less than that a width at a position close to the driving substrate.

6.

发明授权
Chip structure and method for forming the same 有权

公开(公告)号：US11848270B2

公开(公告)日：2023-12-19

申请号：US16422988

申请日：2019-05-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hong-Seng Shue , Sheng-Han Tsai , Kuo-Chin Chang , Mirng-Ji Lii , Kuo-Ching Hsu

IPC分类号： H01L23/528 , H01L23/00 , H01L23/522

CPC分类号： H01L23/5283 , H01L23/5226 , H01L24/08 , H01L24/09 , H01L24/11 , H01L24/16 , H01L24/17 , H01L2224/023 , H01L2224/0224 , H01L2224/0225 , H01L2224/0231 , H01L2224/0233 , H01L2224/02235 , H01L2224/02245 , H01L2224/02255 , H01L2224/02373 , H01L2224/02381 , H01L2224/0401 , H01L2224/081 , H01L2224/0805 , H01L2224/08052 , H01L2224/08113 , H01L2224/16104

摘要： A chip structure is provided. The chip structure includes a substrate. The chip structure includes a redistribution layer over the substrate. The chip structure includes a bonding pad over the redistribution layer. The chip structure includes a shielding pad over the redistribution layer and surrounding the bonding pad. The chip structure includes an insulating layer over the redistribution layer and the shielding pad. The chip structure includes a bump over the bonding pad and the insulating layer. A sidewall of the bump is over the shielding pad.

7.

发明公开
PACKAGE-ON-PACKAGE (POP) TYPE SEMICONDUCTOR PACKAGES 审中-公开

公开(公告)号：US20230223387A1

公开(公告)日：2023-07-13

申请号：US18185526

申请日：2023-03-17

申请人： Samsung Electronics Co., Ltd.

发明人： Minho Lee , Jaewook Yoo

IPC分类号： H01L25/10 , H01L21/48 , H01L23/544 , H01L23/498 , B81C99/00 , H01L25/075 , H01L25/065 , H01L25/00 , H01L23/31 , H01L23/13 , H01L25/16 , H01L25/04 , H01L25/07

CPC分类号： H01L25/105 , H01L21/4857 , H01L23/544 , H01L23/49838 , B81C99/007 , H01L25/0756 , H01L25/0657 , H01L25/50 , H01L23/3128 , H01L23/49816 , H01L23/13 , H01L25/162 , H01L25/043 , H01L25/074 , H01L2224/0213 , H01L2224/75753 , H01L2225/1035 , H01L2223/5442 , H01L2224/0217 , H01L2224/0224 , H01L2225/1058 , H01L2223/54426

摘要： Provided are package-on-package (POP)-type semiconductor packages including a lower package having a first size and including a lower package substrate in which a lower semiconductor chip is, an upper redistribution structure on the lower package substrate and the lower semiconductor chip, and alignment marks. The packages may also include an upper package having a second size smaller than the first size and including an upper package substrate and an upper semiconductor chip. The upper package substrate may be mounted on the upper redistribution structure of the lower package and electrically connected to the lower package, and the upper semiconductor chip may be on the upper package substrate. The alignment marks may be used for identifying the upper package, and the alignment marks may be below and near outer boundaries of the upper package on the lower package.