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30 条记录 (耗时 0.022 秒)

    Method of fabricating an interconnection structure in a CMOS comprising a step of forming a dummy electrode
    4.
    发明授权
    Method of fabricating an interconnection structure in a CMOS comprising a step of forming a dummy electrode 有权
    在CMOS中制造互连结构的方法，包括形成虚拟电极的步骤

    公开(公告)号：US09105692B2

    公开(公告)日：2015-08-11

    申请号：US14058487

    申请日：2013-10-21

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry-Hak-Lay Chuang

    IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

    CPC分类号： H01L21/768 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823871 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for fabricating an interconnection structure in a complementary metal-oxide-semiconductor (CMOS) includes forming an opening in a dielectric layer over a substrate and forming a dummy electrode in a first portion of the opening in the dielectric layer. The method further includes filling a second portion of the opening with a second work-function metal layer, wherein a top surface of the second work-function metal layer is below a top surface of the opening and removing the dummy electrode. The method further includes depositing a first work-function metal layer in the first and second portions, whereby the first work-function metal layer is over the second work-function metal layer in the opening and depositing a signal metal layer over the first work-function metal layer in the first and second portions.

    摘要翻译： 在互补金属氧化物半导体（CMOS）中制造互连结构的方法包括在基板上形成电介质层中的开口，并在电介质层的开口的第一部分中形成虚设电极。 该方法还包括用第二功函数金属层填充开口的第二部分，其中第二功函数金属层的顶表面在开口的顶表面下方并且去除虚拟电极。 该方法还包括在第一和第二部分中沉积第一功函数金属层，由此第一功函数金属层位于开口中的第二功函数金属层上方，并在第一工作金属层上沉积信号金属层， 功能金属层在第一和第二部分。

    Spacer structures of a semiconductor device
    5.
    发明授权
    Spacer structures of a semiconductor device 有权
    半导体器件的间隔结构

    公开(公告)号：US08772147B2

    公开(公告)日：2014-07-08

    申请号：US14032811

    申请日：2013-09-20

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Lee-Wee Teo ,  Ming Zhu ,  Hui-Wen Lin ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

    IPC分类号： H01L29/40 ,  H01L21/8234 ,  H01L21/8238

    CPC分类号： H01L29/401 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088

    摘要： A method of fabricating a semiconductor device includes forming a first set of gate electrodes over a substrate, adjacent gate electrodes of the first set of gate electrodes being separated by a first gap width, and having a first gate width. The method includes forming a second set of gate electrodes over the substrate, adjacent gate electrodes of the second set of gate electrodes being separated by a second gap width less than the first gap width, and having a second gate width greater than the first gate width. The method further includes forming a first set of spacer structures on sidewalls of the first and second sets of gate electrodes. The method further includes forming a second set of spacer structures abutting the first set of spacer structures and removing a subset of the second set of spacer structures over the sidewalls of the second set of gate electrodes.

    摘要翻译： 制造半导体器件的方法包括在衬底上形成第一组栅电极，第一组栅电极的相邻栅电极被第一间隙宽度隔开，并具有第一栅极宽度。 该方法包括在衬底上形成第二组栅极电极，第二组栅极电极的相邻栅电极被第二间隙宽度分开，第二间隙宽度小于第一间隙宽度，并且具有大于第一栅极宽度的第二栅极宽度 。 该方法还包括在第一和第二组栅电极的侧壁上形成第一组间隔结构。 该方法还包括形成邻接第一组间隔结构的第二组间隔结构，并且在第二组栅电极的侧壁上除去第二组间隔结构的子集。

    Method and Apparatus of Forming ESD Protection Device
    6.
    发明申请
    Method and Apparatus of Forming ESD Protection Device 有权
    形成ESD保护装置的方法和装置

    公开(公告)号：US20140038376A1

    公开(公告)日：2014-02-06

    申请号：US14058390

    申请日：2013-10-21

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Ming Zhu ,  Lee-Wee Teo ,  Harry Hak-Lay Chuang

    IPC分类号： H01L29/66

    CPC分类号： H01L29/66484 ,  H01L21/8234 ,  H01L23/60 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides a semiconductor device having a transistor. The transistor includes a source region, a drain region, and a channel region that are formed in a semiconductor substrate. The channel region is disposed between the source and drain regions. The transistor includes a first gate that is disposed over the channel region. The transistor includes a plurality of second gates that are disposed over the drain region.

    摘要翻译： 本公开提供了具有晶体管的半导体器件。 晶体管包括形成在半导体衬底中的源极区，漏极区和沟道区。 沟道区域设置在源区和漏区之间。 晶体管包括设置在沟道区域上的第一栅极。 晶体管包括设置在漏区上的多个第二栅极。

    Method of fabricating hybrid impact-ionization semiconductor device
    8.
    发明授权
    Method of fabricating hybrid impact-ionization semiconductor device 有权
    制造混合冲击电离半导体器件的方法

    公开(公告)号：US09525040B2

    公开(公告)日：2016-12-20

    申请号：US14188181

    申请日：2014-02-24

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Ming Zhu ,  Lee-Wee Teo ,  Harry Hak-Lay Chuang

    IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/423 ,  H01L29/739 ,  H01L21/8238

    CPC分类号： H01L29/66484 ,  H01L21/823807 ,  H01L29/423 ,  H01L29/7391

    摘要： A method includes providing a semiconductor substrate having an active region and forming an isolation structure to isolate the active region. First and second gate structures are formed over the active region. First and second doped regions are formed within the active region of the substrate, the first doped region has a first conductivity type, the second doped region has the second conductivity type. The first and second gate structures are interposed between the first and second doped regions.

    摘要翻译： 一种方法包括提供具有活性区域并形成隔离结构以隔离有源区的半导体衬底。 第一和第二栅极结构形成在有源区上。 第一和第二掺杂区形成在衬底的有源区内，第一掺杂区具有第一导电类型，第二掺杂区具有第二导电类型。 第一和第二栅极结构被插入在第一和第二掺杂区域之间。