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    Integrated circuit with dummy boundary cells
    1.
    发明授权
    Integrated circuit with dummy boundary cells 有权

    公开(公告)号：US11941338B2

    公开(公告)日：2024-03-26

    申请号：US17873699

    申请日：2022-07-26

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Wei-Yi Hu ,  Chih-Ming Chao ,  Chi-Yeh Yu

    IPC: G06F30/392 ,  G06F30/398 ,  H01L27/02 ,  H01L29/423 ,  G06F115/08

    CPC classification number: G06F30/392 ,  G06F30/398 ,  H01L27/0207 ,  H01L29/42376 ,  G06F2115/08

    Abstract: Integrated circuits (IC) are provided. An IC includes a plurality of macros and a top channel. Each macro includes a macro boundary and a main pattern surrounded by the macro boundary. The top channel includes a plurality of first and second sub-channels. Each first sub-channel is arranged between a first macro and a second macro, and is formed by a plurality of first dummy boundary cells. Each second sub-channel is arranged between two of the second macros, and is formed by a plurality of second dummy boundary cells. The macro boundaries of the first macros are formed by the first dummy boundary cells, and the macro boundaries of the second macros are formed by the second dummy boundary cells. A first gate length of dummy patterns within the first dummy boundary cells is greater than a second gate length of dummy patterns within the second dummy boundary cells.

    System, method and associated computer readable medium for designing integrated circuit with pre-layout RC information
    4.
    发明授权
    System, method and associated computer readable medium for designing integrated circuit with pre-layout RC information 有权

    公开(公告)号：US10127338B2

    公开(公告)日：2018-11-13

    申请号：US14969647

    申请日：2015-12-15

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    Inventor： Chin-Sheng Chen ,  Ching-Yu Chai ,  Wei-Yi Hu

    IPC: G06F17/50

    Abstract: A system for designing an integrated circuit having pre-layout RC information is disclosed. The system includes: at least one processor; and at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to: generate current and voltage information for a schematic having device array layout constraint included; create interconnection topology patterns and realizing route for the schematic; generate RC information according to the route; and determine if the schematic having the device array layout constraint and the RC information included violates one or more of the system design rule constraints. An associated method and a computer readable medium are also disclosed.

    In-phase grouping for voltage-dependent design rule
    5.
    发明授权
    In-phase grouping for voltage-dependent design rule 有权
    电压相关设计规则的同相分组

    公开(公告)号：US08943454B1

    公开(公告)日：2015-01-27

    申请号：US14072171

    申请日：2013-11-05

    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

    Inventor： Chih Chi Hsiao ,  Jill Liu ,  Wei-Yi Hu ,  Jui-Feng Kuan ,  Yu-Ren Chen ,  Kuo-Ji Chen ,  Jian-Yi Li ,  Wen-Ju Yang

    IPC: G06F17/50

    CPC classification number: G06F17/5081

    Abstract: In some embodiments, in a method for considering in-phase grouping for a voltage-dependent design rule, for a first net and a second net in a schematic, first data for obtaining the differences between first voltage values of the first and second nets, and between second voltage values of the first and second nets is provided. For each of the first and second nets, the first voltage value is larger than the second voltage value. A layout for the schematic is generated. In the layout, a relationship of a first shape and a second shape associated with the first and the second nets, respectively, is defined using the first data.

    Abstract translation: 在一些实施例中，在用于考虑电压相关设计规则的同相分组的方法中，对于用于获得第一和第二网络的第一电压值之间的差异的用于示意图中的第一网络和第二网络的第一数据， 并且提供第一和第二网络的第二电压值之间。 对于第一和第二网络中的每一个，第一电压值大于第二电压值。 生成原理图的布局。 在布局中，分别使用第一数据来定义与第一和第二网络相关联的第一形状和第二形状的关系。

    Integrated circuit modeling method using resistive capacitance information
    6.
    发明授权
    Integrated circuit modeling method using resistive capacitance information 有权

    公开(公告)号：US09996643B2

    公开(公告)日：2018-06-12

    申请号：US14543352

    申请日：2014-11-17

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Chin-Sheng Chen ,  Tsun-Yu Yang ,  Wei-Yi Hu ,  Jui-Feng Kuan ,  Ching-Shun Yang

    IPC: G06F17/50

    CPC classification number: G06F17/5022 ,  G06F17/5045 ,  G06F2217/74

    Abstract: A method of modeling an integrated circuit comprises generating a schematic of an integrated circuit comprising a first circuit component. The schematic comprises a first representation of the first circuit component. The method also comprises replacing the first representation with a second representation of the first circuit component. The second representation includes resistive capacitance information (RC) for the first circuit component. The RC information is based on first RC data included in a process design kit (PDK) file and second RC data included in a macro device file. The second RC data is based on a relationship between the first circuit component and a second circuit component. The method further comprises selectively coloring the second representation of the first circuit component in the schematic based on the RC information. The coloring of the second representation is indicative of whether the integrated circuit is in compliance with a design specification.

    Track-based fill (TBF) method for metal patterning
    7.
    发明授权
    Track-based fill (TBF) method for metal patterning 有权

    公开(公告)号：US11556691B2

    公开(公告)日：2023-01-17

    申请号：US16573698

    申请日：2019-09-17

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Wei-Yi Hu ,  Chih-Ming Chao ,  Jung-Chou Tsai

    IPC: G06F30/398 ,  G03F1/36 ,  G06F30/392

    Abstract: Disclosed are methods for designing semiconductor devices, conductive layer patterns, and interconnection layer patterns including the operations of analyzing an initial semiconductor design layout to identify excessive open spaces between adjacent conductive elements or lines within an interconnection layer pattern, selecting or generating a dummy pattern to fill a portion of the open space, and generating a modified semiconductor design layout that incorporates the dummy pattern into first interconnection layer pattern to reduce the open space.

    Integrated circuit design flow with device array layout generation
    9.
    发明授权
    Integrated circuit design flow with device array layout generation 有权
    集成电路设计流程与设备阵列布局生成

    公开(公告)号：US09092589B2

    公开(公告)日：2015-07-28

    申请号：US14193527

    申请日：2014-02-28

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Ching-Yu Chai ,  Chin-Sheng Chen ,  Wei-Yi Hu ,  Jui-Feng Kuan

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5068 ,  G06F17/5072

    Abstract: A system for designing an integrated circuit generates a schematic of the integrated circuit based on a set of system design rule constraints. The system also receives a proposed device array layout from a device array design module. The device array design module is configured to generate the proposed device array layout free from the set of system design rule constraints. The system further generates a revised schematic of the integrated circuit including the proposed device array layout. The system additionally determines if the revised schematic violates one or more of the system design rule constraints.

    Abstract translation: 用于设计集成电路的系统基于一组系统设计规则约束产生集成电路的示意图。 该系统还从设备阵列设计模块接收提出的器件阵列布局。 器件阵列设计模块被配置为生成所提出的器件阵列布局，而不受系统设计规则约束的约束。 该系统进一步产生包括所提出的器件阵列布局的集成电路的修改示意图。 该系统另外确定修改后的原理图是否违反了系统设计规则约束中的一个或多个。

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