公开(公告)号：US20240363682A1

公开(公告)日：2024-10-31

申请号：US18771613

申请日：2024-07-12

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jen-Yuan CHANG ,  Chien-Chang LEE ,  Chia-Ping LAI ,  Tzu-Chung TSAI

IPC分类号： H01L23/00 ,  H01L21/56

CPC分类号： H01L28/91 ,  H01L21/56 ,  H01L24/80 ,  H01L2224/80895 ,  H01L2224/80896

摘要： A three-dimensional device structure includes a first die including a first semiconductor substrate, a second die disposed on the first die and including a second semiconductor substrate, a dielectric encapsulation (DE) layer disposed on the first die and surrounding the second die, a redistribution layer structure disposed on the second die and the DE layer, and an integrated passive device (IPD) formed within in the DE layer and electrically connected to the first die and the redistribution layer structure.

公开(公告)号：US20230387089A1

公开(公告)日：2023-11-30

申请号：US18230147

申请日：2023-08-03

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jen-Yuan CHANG ,  Chia-Ping LAI

IPC分类号： H01L25/10 ,  H01L25/00

CPC分类号： H01L25/105 ,  H01L25/50 ,  H01L25/0657

摘要： A semiconductor package includes a first connection die including a semiconductor substrate and an interconnect structure, and a first die stack disposed on the first connection die and including stacked dies, each of the stacked dies including a semiconductor substrate and an interconnect structure including a first connection line that is electrically connected to the interconnect structure of the first connection die. An angle formed between a plane of the first connection die and a plane of each stacked die ranges from about 45° to about 90°.

公开(公告)号：US20240312931A1

公开(公告)日：2024-09-19

申请号：US18669577

申请日：2024-05-21

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jen-Yuan CHANG ,  Chien-Chang LEE ,  Chia-Ping LAI

IPC分类号： H01L23/58 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L23/585 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5222 ,  H01L25/0657 ,  H01L23/562 ,  H01L25/18 ,  H01L2225/06544

摘要： A die includes: a semiconductor substrate; an interconnect structure disposed on the semiconductor substrate and including: inter-metal dielectric (IMD) layers; metal features embedded in the IMD layers; and a guard ring structure including concentric first and second guard rings that extend through at least a subset of the IMD layers; and a through silicon via (TSV) structure extending through the semiconductor substrate and the subset of IMD layers to electrically contact one of the metal features. The first guard ring surrounds the TSV structure; and the second guard ring surrounds the first guard ring and is configured to reduce a parasitic capacitance between the guard ring structure and the TSV structure.

公开(公告)号：US20230069315A1

公开(公告)日：2023-03-02

申请号：US17446053

申请日：2021-08-26

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jen-Yuan CHANG ,  Chien-Chang LEE ,  Chia-Ping LAI ,  Tzu-Chung TSAI

IPC分类号： H01L49/02 ,  H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498

摘要： A three-dimensional device structure includes a die including a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, a through silicon via (TSV) structure that extends through the semiconductor substrate and electrically contacts a metal feature of the interconnect structure, and an integrated passive device (IPD) embedded in the semiconductor substrate and electrically connected to the TSV structure.

公开(公告)号：US20220336684A1

公开(公告)日：2022-10-20

申请号：US17853998

申请日：2022-06-30

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chen-Hao HUANG ,  Hau-Yan LU ,  Sui-Ying HSU ,  YuehYing LEE ,  Chien-Ying WU ,  Chia-Ping LAI

IPC分类号： H01L31/0203 ,  H01L31/0352 ,  H01L31/18 ,  H01L31/105 ,  H01L31/103 ,  H01L31/0312

摘要： At least one doped silicon region is formed in a silicon layer of a semiconductor substrate, and a silicon oxide layer is formed over the silicon layer. A germanium-containing material portion is formed in the semiconductor substrate to provide a p-n junction or a p-i-n junction including the germanium-containing material portion and one of the at least one doped silicon region. A capping material layer that is free of germanium is formed over the germanium-containing material portion. A first dielectric material layer is formed over the silicon oxide layer and the capping material layer. The first dielectric material layer includes a mesa region that is raised from the germanium-containing material portion by a thickness of the capping material layer. The capping material layer may be a silicon capping layer, or may be subsequently removed to form a cavity. Dark current is reduced for the germanium-containing material portion.

公开(公告)号：US20220302050A1

公开(公告)日：2022-09-22

申请号：US17474327

申请日：2021-09-14

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jen-Yuan CHANG ,  Chia-Ping LAI

IPC分类号： H01L23/58 ,  H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

摘要： A semiconductor package includes: a first die; a second die stacked on an upper surface of the first die, the second die including a second semiconductor substrate and a second seal ring structure that extends along a perimeter of the second semiconductor substrate; a third die stacked on the upper surface of the first die, the third die including a third semiconductor substrate and a third seal ring structure that extends along a perimeter of the third semiconductor substrate; and a connection circuit that extends through the second seal ring structure and the third seal ring structure, in a lateral direction perpendicular to the stacking direction of the first die and the second die, to electrically connect the second semiconductor substrate and the third semiconductor substrate.

公开(公告)号：US20230395574A1

公开(公告)日：2023-12-07

申请号：US18366752

申请日：2023-08-08

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jen-Yuan CHANG ,  Chia-Ping LAI

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L21/78

CPC分类号： H01L25/0657 ,  H01L24/08 ,  H01L24/32 ,  H01L24/83 ,  H01L21/78 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/08145 ,  H01L2224/32145 ,  H01L2224/83894 ,  H01L25/0652

摘要： A semiconductor die stack includes a first semiconductor die having a first lattice direction, and a second semiconductor die bonded to the first semiconductor die and having a second lattice direction different than the first lattice direction.

公开(公告)号：US20230378247A1

公开(公告)日：2023-11-23

申请号：US18229612

申请日：2023-08-02

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jen-Yuan CHANG ,  Chien-Chang LEE ,  Chia-Ping LAI ,  Tzu-Chung TSAI

IPC分类号： H10N69/00 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065 ,  H01L23/498

CPC分类号： H01L28/90 ,  H01L24/08 ,  H01L23/481 ,  H01L24/32 ,  H01L24/33 ,  H01L25/0657 ,  H01L23/49816 ,  H01L2225/06541 ,  H01L2224/09181 ,  H01L2224/33181 ,  H01L2224/08146 ,  H01L2224/32145

摘要： A three-dimensional device structure includes a die including a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, a through silicon via (TSV) structure that extends through the semiconductor substrate and electrically contacts a metal feature of the interconnect structure, and an integrated passive device (IPD) embedded in the semiconductor substrate and electrically connected to the TSV structure.

公开(公告)号：US20230067714A1

公开(公告)日：2023-03-02

申请号：US17412469

申请日：2021-08-26

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jen-Yuan CHANG ,  Chien-Chang LEE ,  Chia-Ping LAI

IPC分类号： H01L23/10 ,  H01L23/535 ,  H01L23/60 ,  H01L23/538 ,  H01L23/522 ,  H01L27/06

摘要： A three-dimensional device structure includes a first die, a second die disposed on the first die, and a connection circuit. The first die includes a first semiconductor substrate, a first interconnect structure disposed on the first semiconductor substrate, and a first seal surrounding the interconnect structure. The second die includes a second semiconductor substrate, a second interconnect structure disposed on the second semiconductor substrate, and a second seal ring surrounding the interconnect structure. The first connection circuit electrically couples the first seal ring to the second seal ring to provide an electrostatic discharge path.

公开(公告)号：US20220310570A1

公开(公告)日：2022-09-29

申请号：US17476703

申请日：2021-09-16

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jen-Yuan CHANG ,  Chia-Ping LAI

IPC分类号： H01L25/10 ,  H01L25/00

摘要： A semiconductor package includes a first connection die including a semiconductor substrate and an interconnect structure, and a first die stack disposed on the first connection die and including stacked dies, each of the stacked dies including a semiconductor substrate and an interconnect structure including a first connection line that is electrically connected to the interconnect structure of the first connection die. An angle formed between a plane of the first connection die and a plane of each stacked die ranges from about 45° to about 90°.