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公开(公告)号:US20150333149A1
公开(公告)日:2015-11-19
申请号:US14809614
申请日:2015-07-27
发明人: Shih-Wen Liu , Mei-Yun Wang , Hsien-Cheng Wang , Fu-Kai Yang , Hsiao-Chiu Hsu , Hsin-Ying Lin
CPC分类号: H01L29/66545 , H01L21/823475 , H01L27/088 , H01L29/0653 , H01L29/401 , H01L29/4175 , H01L29/45 , H01L29/66484 , H01L29/66795
摘要: A semiconductor arrangement and method of formation are provided herein. A semiconductor arrangement includes a metal connect in contact with a first active region and a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes recessing the metal connect over the STI region to form a recessed portion of the metal connect. Forming the recessed portion of the metal connect in contact with the first active region and the second active region mitigates RC coupling, such that a first gate is formed closer to a second gate, thus reducing a size of a chip on which the recessed portion is located.
摘要翻译: 本文提供半导体布置和形成方法。 半导体装置包括与第一有源区和第二有源区接触的金属连接以及位于第一有源区和第二有源区之间的浅沟槽隔离区。 形成半导体装置的方法包括将金属连接凹入到STI区域上以形成金属连接的凹陷部分。 形成与第一有源区域和第二有源区域接触的金属的凹陷部分缓和RC耦合,使得第一栅极形成得更靠近第二栅极,从而减小其上凹陷部分的芯片的尺寸 位于。
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公开(公告)号:US09754838B2
公开(公告)日:2017-09-05
申请号:US15362746
申请日:2016-11-28
发明人: I-Wen Wu , Hsien-Cheng Wang , Mei-Yun Wang , Shih-Wen Liu , Chao-Hsun Wang , Yun Lee
IPC分类号: H01L21/8234 , H01L29/78 , H01L21/84 , H01L27/088 , H01L27/12
CPC分类号: H01L21/823475 , H01L21/823431 , H01L21/823481 , H01L21/823487 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/78
摘要: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.
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公开(公告)号:US09449886B2
公开(公告)日:2016-09-20
申请号:US15130032
申请日:2016-04-15
发明人: I-Wen Wu , Hsien-Cheng Wang , Hsin-Ying Lin , Mei-Yun Wang , Hsiao-Chiu Hsu , Shih-Wen Liu
IPC分类号: H01L21/8238 , H01L21/762 , H01L21/8234
CPC分类号: H01L21/823821 , H01L21/76224 , H01L21/823431 , H01L21/823481 , H01L27/0886 , H01L29/0653 , H01L29/66795 , H01L29/785
摘要: A semiconductor device and method of formation are provided herein. A semiconductor device includes a first active region adjacent a first side of a shallow trench isolation (STI) region. The first active region including a first proximal fin having a first proximal fin height adjacent the STI region, and a first distal fin having a first distal fin height adjacent the first proximal fin, the first proximal fin height less than the first distal fin height. The STI region includes oxide, the oxide having an oxide volume, where the oxide volume is inversely proportional to the first proximal fin height. A method of formation includes forming a first proximal fin with a first proximal fin height less than a first distal fin height of a first distal fin, such that the first proximal fin is situated between the first distal fin and an STI region.
摘要翻译: 本文提供半导体器件和形成方法。 半导体器件包括与浅沟槽隔离(STI)区域的第一侧相邻的第一有源区。 所述第一活动区域包括具有邻近所述STI区域的第一近侧翅片高度的第一近侧翅片以及具有与所述第一近侧翅片相邻的第一远侧翅片高度的第一远侧翅片,所述第一近侧翅片高度小于所述第一远侧翅片高度。 STI区域包括氧化物,氧化物具有氧化物体积,其中氧化物体积与第一近侧翅片高度成反比。 一种形成方法包括形成具有小于第一远侧翅片的第一远侧翅片高度的第一近侧翅片高度的第一近侧翅片,使得第一近侧翅片位于第一远侧翅片和STI区域之间。
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公开(公告)号:US10109530B2
公开(公告)日:2018-10-23
申请号:US15693676
申请日:2017-09-01
发明人: I-Wen Wu , Hsien-Cheng Wang , Mei-Yun Wang , Shih-Wen Liu , Chao-Hsun Wang , Yun Lee
IPC分类号: H01L21/8234 , H01L21/84 , H01L27/088 , H01L27/12 , H01L29/78
摘要: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.
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公开(公告)号:US20170103918A1
公开(公告)日:2017-04-13
申请号:US15384446
申请日:2016-12-20
发明人: Audrey Hsiao-Chiu Hsu , Fu-Kai Yang , Mei-Yun Wang , Hsien-Cheng Wang , Shih-Wen Liu , Hsin-Ying Lin
IPC分类号: H01L21/768 , H01L23/532 , H01L21/285 , H01L23/535
CPC分类号: H01L21/76897 , H01L21/2633 , H01L21/28518 , H01L21/31116 , H01L21/32051 , H01L21/32053 , H01L21/32105 , H01L21/3212 , H01L21/76805 , H01L21/76831 , H01L21/7684 , H01L21/823425 , H01L21/823475 , H01L23/485 , H01L23/53261 , H01L23/53266 , H01L23/535 , H01L27/088 , H01L29/4933 , H01L29/665 , H01L29/6656 , H01L2924/0002 , H01L2924/00
摘要: A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate are etched to expose an underlying silicon substrate. A silicide portion defined by a contact profile is deposited in the exposed portion of the silicon substrate. A second sidewall layer substantially covers the first sidewall layer and at least partially covering the silicide portion is formed after depositing the silicide portion. A metal glue layer is deposited around the first metal gate and the second metal gate defining a trench above the silicide portion. A metal plug is deposited within the trench.
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公开(公告)号:US20150194516A1
公开(公告)日:2015-07-09
申请号:US14148172
申请日:2014-01-06
发明人: I-Wen Wu , Mei-Yun Wang , Hsien-Cheng Wang , Shih-Wen Liu , Yun Lee , Chao-Hsun Wang
CPC分类号: H01L21/823475 , H01L21/823431 , H01L21/823481 , H01L21/823487 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/78
摘要: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.
摘要翻译: 对半导体装置及其形成方法进行说明。 半导体装置包括与第一有源区中的第一金属连接和第二有源区中的第二金属连接以及位于第一有源区和第二有源区之间的浅沟槽隔离区之间的第三金属连接。 形成半导体装置的方法包括在第一金属连接件,STI区域和第二金属连接件上形成第一开口,并在第一开口中形成第三金属连接件。 形成第三个金属连接在第一个金属连接和第二个金属连接减轻RC耦合。
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公开(公告)号:US20150194425A1
公开(公告)日:2015-07-09
申请号:US14147851
申请日:2014-01-06
发明人: I-Wen Wu , Mei-Yun Wang , Hsien-Cheng Wang , Shih-Wen Liu , Hsiao-Chiu Hsu , Hsin-Ying Lin
IPC分类号: H01L27/088 , H01L21/8234 , H01L21/762 , H01L29/06
CPC分类号: H01L21/823821 , H01L21/76224 , H01L21/823431 , H01L21/823481 , H01L27/0886 , H01L29/0653 , H01L29/66795 , H01L29/785
摘要: A semiconductor device and method of formation are provided herein. A semiconductor device includes a first active region adjacent a first side of a shallow trench isolation (STI) region. The first active region including a first proximal fin having a first proximal fin height adjacent the STI region, and a first distal fin having a first distal fin height adjacent the first proximal fin, the first proximal fin height less than the first distal fin height. The STI region includes oxide, the oxide having an oxide volume, where the oxide volume is inversely proportional to the first proximal fin height. A method of formation includes forming a first proximal fin with a first proximal fin height less than a first distal fin height of a first distal fin, such that the first proximal fin is situated between the first distal fin and an STI region.
摘要翻译: 本文提供半导体器件和形成方法。 半导体器件包括与浅沟槽隔离(STI)区域的第一侧相邻的第一有源区。 所述第一活动区域包括具有邻近所述STI区域的第一近侧翅片高度的第一近侧翅片以及具有与所述第一近侧翅片相邻的第一远侧翅片高度的第一远侧翅片,所述第一近侧翅片高度小于所述第一远侧翅片高度。 STI区域包括氧化物,氧化物具有氧化物体积,其中氧化物体积与第一近侧翅片高度成反比。 一种形成方法包括形成具有小于第一远侧翅片的第一远侧翅片高度的第一近侧翅片高度的第一近侧翅片,使得第一近侧翅片位于第一远侧翅片和STI区域之间。
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公开(公告)号:US20150194422A1
公开(公告)日:2015-07-09
申请号:US14148251
申请日:2014-01-06
发明人: Shih-Wen Liu , Mei-Yun Wang , Hsien-Cheng Wang , Fu-Kai Yang , Hsiao-Chiu Hsu , Hsin-Ying Lin
IPC分类号: H01L27/088 , H01L29/06 , H01L21/8234 , H01L23/64 , H01L29/45 , H01L29/417
CPC分类号: H01L29/66545 , H01L21/823475 , H01L27/088 , H01L29/0653 , H01L29/401 , H01L29/4175 , H01L29/45 , H01L29/66484 , H01L29/66795
摘要: A semiconductor arrangement and method of formation are provided herein. A semiconductor arrangement includes a metal connect in contact with a first active region and a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes recessing the metal connect over the STI region to form a recessed portion of the metal connect. Forming the recessed portion of the metal connect in contact with the first active region and the second active region mitigates RC coupling, such that a first gate is formed closer to a second gate, thus reducing a size of a chip on which the recessed portion is located.
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公开(公告)号:US10510614B2
公开(公告)日:2019-12-17
申请号:US16396966
申请日:2019-04-29
发明人: I-Wen Wu , Hsien-Cheng Wang , Mei-Yun Wang , Shih-Wen Liu , Chao-Hsun Wang , Yun Lee
IPC分类号: H01L21/8234 , H01L29/78 , H01L21/84 , H01L27/088 , H01L27/12
摘要: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.
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公开(公告)号:US10276448B2
公开(公告)日:2019-04-30
申请号:US16166238
申请日:2018-10-22
发明人: I-Wen Wu , Hsien-Cheng Wang , Mei-Yun Wang , Shih-Wen Liu , Chao-Hsun Wang , Yun Lee
IPC分类号: H01L21/8234 , H01L29/78 , H01L21/84 , H01L27/088 , H01L27/12
摘要: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.
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