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公开(公告)号：US07009246B2
公开(公告)日：2006-03-07
申请号：US10772391
申请日：2004-02-06
IPC分类号： H01L29/72
CPC分类号： H01L27/088 , G11C11/412 , H01L27/0928 , H01L27/1104
摘要： To reduce the width of isolation between the first and second p channel MIS•FETs driven by different voltages, a first p channel MIS•FET driven by a first supply voltage and a second p channel MIS•FET driven by a second supply voltage higher than the first supply voltage are arranged in the same n well of the same semiconductor substrate, and the second supply voltage is supplied as a common well bias voltage to the n well.
摘要翻译： 为了减小由不同电压驱动的第一和第二p沟道MIS.FET之间的隔离宽度，由第一电源电压驱动的第一p沟道MIS.FET和由第二电源电压高于 第一电源电压被布置在相同半导体衬底的相同n阱中，并且第二电源电压作为公共阱偏置电压被提供给n阱。
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公开(公告)号：US06920071B2
公开(公告)日：2005-07-19
申请号：US10845270
申请日：2004-05-14
IPC分类号： G11C11/417 , G11C7/00 , G11C8/00 , G11C8/08 , G11C11/413 , G11C11/418 , H01L21/8234 , H01L21/8244 , H01L27/088 , H01L27/10 , H01L27/11 , H03K5/153 , H03K19/0185
CPC分类号： G11C11/413 , G11C8/08 , G11C11/418 , H03K19/018521
摘要： A semiconductor integrated circuit device endowed with memory circuits achieving high operation margin and low energy consumption with high speed and high integration. Composing a memory cell with a MOSFET having a first threshold voltage corresponding to a first voltage and supplying a selection signal corresponding to said first voltage to a word line by a word driver driven at said first voltage. Corresponding to a second voltage smaller than said first voltage, forming a selection signal sending to said word driver by a decoder comprising MOSFET with a second threshold voltage smaller than said first voltage, operating at said first voltage, and installing a first level shifting circuit including inverter circuits that form a selection signal corresponding to said first voltage by receiving a selection signal corresponding to said second voltage. Thereby, high operation margin and low energy consumption with high speed and high integration can be achieved.
摘要翻译： 一种半导体集成电路器件，具有高速高集成度的高运算裕度和低能耗的存储电路。 用具有对应于第一电压的第一阈值电压的MOSFET构成存储单元，并且通过由所述第一电压驱动的字驱动器将对应于所述第一电压的选择信号提供给字线。 对应于小于所述第一电压的第二电压，形成由包括具有小于所述第一电压的第二阈值电压的MOSFET的解码器向所述字驱动器发送的选择信号，在所述第一电压下操作，并且安装第一电平移位电路，包括 逆变器电路，通过接收对应于所述第二电压的选择信号，形成对应于所述第一电压的选择信号。 因此，可以实现高运行裕度和低能耗，高速度和高集成度。
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公开(公告)号：US20050002224A1
公开(公告)日：2005-01-06
申请号：US10845270
申请日：2004-05-14
IPC分类号： G11C11/417 , G11C7/00 , G11C8/00 , G11C8/08 , G11C11/413 , G11C11/418 , H01L21/8234 , H01L21/8244 , H01L27/088 , H01L27/10 , H01L27/11 , H03K5/153 , H03K19/0185
CPC分类号： G11C11/413 , G11C8/08 , G11C11/418 , H03K19/018521
摘要： A semiconductor integrated circuit device endowed with memory circuits achieving high operation margin and low energy consumption with high speed and high integration. Composing a memory cell with a MOSFET having a first threshold voltage corresponding to a first voltage and supplying a selection signal corresponding to said first voltage to a word line by a word driver driven at said first voltage. Corresponding to a second voltage smaller than said first voltage, forming a selection signal sending to said word driver by a decoder comprising MOSFET with a second threshold voltage smaller than said first voltage, operating at said first voltage, and installing a first level shifting circuit including inverter circuits that form a selection signal corresponding to said first voltage by receiving a selection signal corresponding to said second voltage. Thereby, high operation margin and low energy consumption with high speed and high integration can be achieved.
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4.发明申请公开(公告)号：US20050007170A1
公开(公告)日：2005-01-13
申请号：US10885018
申请日：2004-07-07
CPC分类号： G11C7/22 , G11C7/1075
摘要： An asynchronous control circuit and a semiconductor integrated circuit achieving asynchronous operation and no limitation on the number of ports are offered. In an asynchronous control circuit, by being activated corresponding to at least one access request by acknowledging a plurality of access request signals generated asynchronously to each other and a plurality of input signals corresponding to each of the above-mentioned plurality of access requests, selecting one access request from one or more access requests in the activation mode, acknowledging an input signal corresponding thereto, transmitting the input signal to a memory, acknowledging the input signal corresponding to a non-executed access request after the end the operation corresponding to the input signal, and accessing the aforementioned memory circuit.
摘要翻译： 提供异步控制电路和实现异步操作的半导体集成电路，并且不限制端口数量。 在异步控制电路中，通过响应于至少一个接入请求被激活，确认彼此异步生成的多个接入请求信号和对应于上述多个接入请求中的每一个的多个输入信号，选择一个 在激活模式下从一个或多个访问请求访问请求，确认与其对应的输入信号，将输入信号发送到存储器，在结束对应于输入信号的操作结束之后确认对应于未执行访问请求的输入信号 ，并访问上述存储电路。
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公开(公告)号：US07012848B2
公开(公告)日：2006-03-14
申请号：US10917320
申请日：2004-08-13
IPC分类号： G11C7/00
CPC分类号： G11C7/1069 , G11C7/1051 , G11C8/16 , G11C11/4125
摘要： The present invention provides a novel semiconductor integrated circuit device equipped with memory circuits, high-speed memories and large memory capacity memory circuits, which enables speeding up and facilitation of timing settings. The semiconductor integrated circuit device is provided with first amplifier circuits; which include first MOSFETs of first conductivity type, which have gates provided for a plurality of bit lines to which memory cells are respectively connected, and which are respectively maintained in an off state under precharge voltages supplied to the bit lines, as read circuits of the memory cells determined as to whether memory currents flow according to the operation of selecting word lines and memory information; and which are respectively brought to operating states in association with select signals for the bit lines, and also provided with a second amplifier circuit including; a plurality of second MOSFETs of second conductivity type, which have gates respectively supplied with a plurality of amplified signals of the first amplifier circuits and which are connected in parallel configurations; and which forms an amplified signal corresponding to the amplified signals of the first amplifier circuits.
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公开(公告)号：US20050146947A1
公开(公告)日：2005-07-07
申请号：US11011427
申请日：2004-12-15
IPC分类号： G11C15/04 , G11C16/04 , H01L21/8244 , H01L27/11
CPC分类号： H01L27/11 , G11C15/04 , G11C15/043 , H01L27/1104
摘要： Data lines (D0, D1) are shared by a first storage portion (MA) and a second storage portion (MB), and furthermore, a first transistor (MC0) coupled to a first comparison data portion (CD0) and a second transistor (MCA) coupled to the storage node of a first storage portion are connected in series to form a first comparing circuit (11), and a third transistor (MC1) coupled to a second comparison data line (CD1) and a fourth transistor (MCB) coupled to the storage node of the second storage portion are connected in series to form a second comparing circuit (12). Consequently, it is possible to enhance a symmetry in the layout of a diffusion layer and a wiring layer and to achieve the easiness of a layout in which a memory cell is line symmetrical with respect to a center line passing through a center thereof. Thus, a manufacturing process condition can easily be optimized and a variation in a manufacturing process can be reduced so that the microfabrication of the memory cell can be achieved.
摘要翻译： 数据线（D 0，D 1）由第一存储部分（MA）和第二存储部分（MB）共享，此外，第一晶体管（MC 0）耦合到第一比较数据部分（CD 0）和 耦合到第一存储部分的存储节点的第二晶体管（MCA）串联连接以形成第一比较电路（11）和耦合到第二比较数据线（CD 1）的第三晶体管（MC 1）和 耦合到第二存储部分的存储节点的第四晶体管（MCB）串联连接以形成第二比较电路（12）。 因此，可以提高扩散层和布线层的布局的对称性，并且实现存储单元相对于穿过其中心的中心线线对称的布局的容易性。 因此，可以容易地优化制造工艺条件，并且可以降低制造工艺的变化，从而可以实现存储单元的微细加工。
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公开(公告)号：US06876573B2
公开(公告)日：2005-04-05
申请号：US10917321
申请日：2004-08-13
申请人： Keiichi Higeta , Shigeru Nakahara , Hiroaki Nambu
发明人： Keiichi Higeta , Shigeru Nakahara , Hiroaki Nambu
IPC分类号： G11C8/02 , G11C11/41 , G11C11/412 , G11C11/413 , G11C11/417 , H01L21/8244 , H01L27/10 , H01L27/11 , G11C11/00
CPC分类号： G11C11/417 , G11C11/412
摘要： A semiconductor memory device having a memory array comprising CMOS flip-flop circuit type memory cells, which is capable of improving a noise margin, making a read rate fast and reducing power consumption. In the semiconductor memory device, an operating voltage of the memory cell is set higher than an operating voltage of each of peripheral circuits. Threshold voltages of MOS transistors that constitute the memory cell, are set higher than those of MOS transistors constituting the peripheral circuit. A gate insulting film for the MOS transistors that constitute the memory cell, is formed so as to be regarded as thicker than a gate insulting film for the MOS transistors constituting the peripheral circuit when converted to an insulating film of the same material. Further, a word-line selection level and a bit-line precharge level are set identical to the level of the operating voltage of the peripheral circuit.
摘要翻译： 一种具有包括CMOS触发器电路型存储单元的存储器阵列的半导体存储器件，其能够提高噪声容限，使得读取速度快并降低功耗。 在半导体存储器件中，将存储单元的工作电压设定得高于外围电路的工作电压。 构成存储单元的MOS晶体管的阈值电压被设定为高于构成外围电路的MOS晶体管的阈值电压。 构成存储单元的MOS晶体管的栅极绝缘膜形成为当被转换为相同材料的绝缘膜时，构成构成外围电路的MOS晶体管的栅极绝缘膜更厚。 此外，字线选择电平和位线预充电电平被设置为与外围电路的工作电压的电平相同。
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公开(公告)号：US06512709B1
公开(公告)日：2003-01-28
申请号：US10173429
申请日：2002-06-18
IPC分类号： G11C700
CPC分类号： G11C29/848 , G11C29/028 , G11C29/44 , G11C29/50012 , G11C29/787 , G11C29/789 , G11C29/802 , G11C2029/1208 , G11C2029/4402
摘要： A semiconductor integrated circuit having therein a plurality of memories, realizing an improved yield by efficiently repairing a defective bit in a memory. This semiconductor integrated circuit has: a plurality of circuit blocks (RAM macro cells) each having an identification code coincidence detecting circuit for determining whether an input identification code coincides with a self identification code or not and a reception data latch and performing an operation according to latched data; a setting circuit capable of setting the identification code and information corresponding to the identification code and serially outputting the set information; and a control circuit capable of sequentially reading the setting information from the setting circuit, converting the setting information to parallel data, and transferring the parallel data to the plurality of circuit blocks. Each of the plurality of circuit blocks captures and holds the setting information transferred when the identification code coincidence detecting circuit determines that the input identification code and the self identification code coincide with each other.
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公开(公告)号：US06445627B1
公开(公告)日：2002-09-03
申请号：US09886026
申请日：2001-06-22
IPC分类号： G11C700
CPC分类号： G11C29/848 , G11C29/028 , G11C29/44 , G11C29/50012 , G11C29/787 , G11C29/789 , G11C29/802 , G11C2029/1208 , G11C2029/4402
摘要： A semiconductor integrated circuit can efficiently repair a defective bit in a memory and comprises a plurality of circuit blocks (RAM macro cells) each having an identification code coincidence detecting circuit for determining whether an input identification code coincides with a self identification code and a reception data latch and performing an operation according to latched data; a setting circuit capable of setting the identification code and information corresponding to the identification code and serially outputting the set information; and a control circuit capable of sequentially reading the set information from the setting circuit, converting the set information to parallel data, and transferring the parallel data to the plurality of circuit blocks. Each of the plurality of circuit blocks captures and holds the set information transferred when the identification code coincidence detecting circuit determines that the input identification code and the self identification code coincide.
摘要翻译： 半导体集成电路可以有效地修复存储器中的有缺陷的位，并且包括多个电路块（RAM宏单元），每个电路块具有识别码重合检测电路，用于确定输入的识别码是否与自身识别码和接收数据一致 锁存并根据锁存数据执行操作; 设置电路，其能够设置与识别码相对应的识别码和信息，并且串行地输出设定信息; 以及控制电路，能够从设定电路依次读取设定信息，将设定信息转换成并行数据，并将并行数据传送给多个电路块。 当识别码一致检测电路确定输入的识别码和自身识别码一致时，多个电路块中的每一个捕获并保持传送的设置信息。
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公开(公告)号：US06791895B2
公开(公告)日：2004-09-14
申请号：US10671475
申请日：2003-09-29
申请人： Keiichi Higeta , Shigeru Nakahara , Hiroaki Nambu
发明人： Keiichi Higeta , Shigeru Nakahara , Hiroaki Nambu
IPC分类号： G11C700
CPC分类号： G11C11/417 , G11C11/412
摘要： A semiconductor memory device having a memory array comprising CMOS flip-flop circuit type memory cells, which is capable of improving a noise margin, making a read rate fast and reducing power consumption. In the semiconductor memory device, an operating voltage of the memory cell is set higher than an operating voltage of each of peripheral circuits. Threshold voltages of MOS transistors that constitute the memory cell, are set higher than those of MOS transistors constituting the peripheral circuit. A gate insulting film for the MOS transistors that constitute the memory cell, is formed so as to be regarded as thicker than a gate insulting film for the MOS transistors constituting the peripheral circuit when converted to an insulating film of the same material. Further, a word-line selection level and a bit-line precharge level are set identical to the level of the operating voltage of the peripheral circuit.
摘要翻译： 一种具有包括CMOS触发器电路型存储单元的存储器阵列的半导体存储器件，其能够提高噪声容限，使得读取速度快并降低功耗。 在半导体存储器件中，将存储单元的工作电压设定得高于外围电路的工作电压。 构成存储单元的MOS晶体管的阈值电压被设定为高于构成外围电路的MOS晶体管的阈值电压。 构成存储单元的MOS晶体管的栅极绝缘膜形成为当被转换为相同材料的绝缘膜时，构成构成外围电路的MOS晶体管的栅极绝缘膜更厚。 此外，字线选择电平和位线预充电电平被设置为与外围电路的工作电压的电平相同。
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