公开(公告)号：US06551398B2

公开(公告)日：2003-04-22

申请号：US09213017

申请日：1998-12-16

申请人： Takao Abe ,  Norihiro Kobayashi ,  Masahiro Kato

发明人： Takao Abe ,  Norihiro Kobayashi ,  Masahiro Kato

IPC分类号： H01L21324

CPC分类号： C30B29/06 ,  C30B33/00 ,  H01L21/3225

摘要： There is disclosed a heat treatment method for a silicon monocrystal wafer comprising the steps of heat-treating in a reducing atmosphere a silicon monocrystal wafer manufactured by growing a silicon monocrystal ingot by Czochralski method wherein a wafer obtained from a silicon monocrystal ingot having oxygen concentration of 16 ppma or less which is manufactured by pulling at a growth rate of 0.6 mm/min or more, and in which COPs exist in high density is subjected to anneal heat treatment at 1200° C. or above for one second or more through use of a rapid heating/rapid cooling apparatus, or at 1200° C. or above for 30 minutes or more through use of a batchwise heat treatment furnace, and no defect silicon monocrystal wafer obtained with the method. There can be manufactured a silicon monocrystal wafer in which crystal defects existing on the surface of the wafer or at the surface layer portion thereof are minimized, and there can be provided a silicon monocrystal wafer for a device which is excellent in electric characteristics such as oxide dielectric breakdown voltage and electrical reliability.

摘要翻译： 公开了一种用于硅单晶晶片的热处理方法，包括以下步骤：在还原性气氛中通过采用Czochralski法生长硅单晶锭制造的硅单晶晶片进行热处理，其中从具有氧浓度的硅单晶锭获得的晶片 通过以0.6mm / min以上的生长速度拉伸制造的16ppma以下，其中以高密度存在COP，在1200℃以上进行退火热处理1秒以上，通过使用 快速加热/快速冷却装置，或者通过使用间歇式热处理炉在1200℃以上30分钟以上，并且没有利用该方法获得的缺陷硅单晶晶片。 可以制造其中存在于晶片表面或其表层部分处的晶体缺陷最小化的硅单晶晶片，并且可以提供具有优异电特性的器件的硅单晶晶片，例如氧化物 介电击穿电压和电气可靠性。

公开(公告)号：US06204188B1

公开(公告)日：2001-03-20

申请号：US08966863

申请日：1997-11-10

申请人： Takao Abe ,  Norihiro Kobayashi

发明人： Takao Abe ,  Norihiro Kobayashi

IPC分类号： H01L21302

CPC分类号： H01L21/3225

摘要： There is disclosed a heat treatment method for a silicon wafer. A silicon wafer, on which a natural oxide film is formed at least at the surface thereof, is loaded directly into a heat treatment furnace heated to a temperature within a temperature range of 1000° C. to the melting point of silicon. Subsequently, the silicon wafer is heat-treated at a temperature within the temperature range, and the silicon wafer having a temperature within the temperature range is unloaded from the heat treatment furnace immediately after the heat treatment is completed. The heat treatment method can be performed at low cost, and can remove crystal defects within a short period of time, with no use of gas endangering safety such as hydrogen.

摘要翻译： 公开了一种硅晶片的热处理方法。 至少在其表面形成有天然氧化物膜的硅晶片被直接加载到加热到1000℃的温度到硅的熔点的热处理炉中。 随后，在温度范围内的温度下对硅晶片进行热处理，并且在热处理完成后立即从热处理炉中卸载具有温度范围内的温度的硅晶片。 热处理方法可以低成本地进行，并且可以在短时间内消除晶体缺陷，而不使用危及诸如氢的安全性的气体。

公开(公告)号：US06333279B1

公开(公告)日：2001-12-25

申请号：US09600819

申请日：2000-07-24

申请人： Norihiro Kobayashi ,  Shoji Akiyama ,  Takao Abe

发明人： Norihiro Kobayashi ,  Shoji Akiyama ,  Takao Abe

IPC分类号： H01L2100

CPC分类号： H01L21/02008 ,  C30B29/06 ,  C30B33/00 ,  H01L21/322

摘要： The present invention provides a method for producing a silicon wafer characterized in that at least one surface of the wafer is subjected to a multi-step polishing process, in which a heat treatment in a mixed gas atmosphere of hydrogen and argon through use of a rapid heating/rapid cooling apparatus is substituted for a final polishing in the multi-step polishing process, and a silicon wafer produced by the method. Thereby, there can be provided a silicon wafer in high productivity wherein there is neither mechanical damages nor scratches on the surface of the wafer, surface roughness is significantly improved, and there is no slip dislocation.

摘要翻译： 本发明提供了一种制造硅晶片的方法，其特征在于，对晶片的至少一个表面进行多步抛光工艺，其中在氢和氩的混合气体气氛中通过使用快速 加热/快速冷却装置代替多步抛光工艺中的最终抛光，以及通过该方法制造的硅晶片。 由此，可以提供高生产率的硅晶片，其中在晶片表面上既不存在机械损伤也不刮伤，表面粗糙度显着提高，并且不存在滑移位错。

公开(公告)号：US06538285B2

公开(公告)日：2003-03-25

申请号：US09983205

申请日：2001-10-23

申请人： Norihiro Kobayashi ,  Shoji Akiyama ,  Takao Abe

发明人： Norihiro Kobayashi ,  Shoji Akiyama ,  Takao Abe

IPC分类号： H01L2701

CPC分类号： H01L21/02008 ,  C30B29/06 ,  C30B33/00 ,  H01L21/322

摘要： The present invention provides a method for producing a silicon wafer characterized in that at least one surface of the wafer is subjected to a multi-step polishing process, in which a heat treatment in a mixed gas atmosphere of hydrogen and argon through use of a rapid heating/rapid cooling apparatus is substituted for a final polishing in the multi-step polishing process, and a silicon wafer produced by the method. Thereby, there can be provided a silicon wafer in high productivity wherein there is neither mechanical damages nor scratches on the surface of the wafer, surface roughness is significantly improved, and there is no slip dislocation.

公开(公告)号：US06403502B1

公开(公告)日：2002-06-11

申请号：US09046996

申请日：1998-03-24

申请人： Norihiro Kobayashi ,  Satoshi Oka ,  Takao Abe

发明人： Norihiro Kobayashi ,  Satoshi Oka ,  Takao Abe

IPC分类号： H01L21324

CPC分类号： H01L21/3225 ,  Y10S438/905

摘要： There is disclosed a heat treatment method for a silicon wafer in which the silicon wafer is heat treated in a reducing atmosphere through use of a rapid heating/rapid cooling apparatus. The silicon wafer is heat treated for a period of 1 to 60 seconds at a temperature in the range of 1200° C. to the melting temperature of silicon. The heat treatment method can reduce the density of COPs and micro-defects which serve as nuclei of oxidation induced stacking faults at the surface of the silicon wafer.

摘要翻译： 公开了通过使用快速加热/快速冷却装置在还原气氛中对硅晶片进行热处理的硅晶片的热处理方法。 将硅晶片在1200℃的温度下对硅的熔融温度进行1〜60秒的时间热处理。 热处理方法可以降低作为硅晶片表面的氧化诱导堆垛层错核的COP和微缺陷的密度。

公开(公告)号：US20120326268A1

公开(公告)日：2012-12-27

申请号：US13582614

申请日：2011-03-01

申请人： Masahiro Kato ,  Satoshi Oka ,  Norihiro Kobayashi ,  Tohru Ishizuka ,  Nobuhiko Noto

发明人： Masahiro Kato ,  Satoshi Oka ,  Norihiro Kobayashi ,  Tohru Ishizuka ,  Nobuhiko Noto

IPC分类号： H01L29/06 ,  H01L21/20 ,  H01L21/762 ,  H01L29/02

CPC分类号： H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/76254 ,  H01L29/78603

摘要： A silicon epitaxial wafer having a silicon epitaxial layer grown by vapor phase epitaxy on a main surface of a silicon single crystal substrate, wherein the main surface of the silicon single crystal substrate is tilted with respect to a [100] axis at an angle θ in a [011] direction or a [0-1-1] direction from a (100) plane and at an angle Φ in a [01-1] direction or a [0-11] direction from the (100) plane, the angle θ and the angle Φ are less than ten minutes, and a dopant concentration of the silicon epitaxial layer is equal to or more than 1×1019/cm3. Even when an epitaxial layer having a dopant concentration of 1×1019/cm3 or more is formed on the main surface of the silicon single crystal substrate, stripe-shaped surface irregularities on the epitaxial layer are inhibited.

摘要翻译： 一种硅外延片，其具有在硅单晶衬底的主表面上通过气相外延生长的硅外延层，其中所述硅单晶衬底的主表面相对于[100]轴以角度倾斜; 在（100）面的[011]方向或[0-1-1]方向上，在（100）面的[01-1]方向或[0-11]方向上的角度Φ处， 角度和角度 角度Φ小于10分钟，硅外延层的掺杂剂浓度为1×1019 / cm3以上。 即使在硅单晶衬底的主表面上形成掺杂浓度为1×1019 / cm3以上的外延层，也抑制了外延层上的条状表面凹凸。

公开(公告)号：US08823130B2

公开(公告)日：2014-09-02

申请号：US13582614

申请日：2011-03-01

申请人： Masahiro Kato ,  Satoshi Oka ,  Norihiro Kobayashi ,  Tohru Ishizuka ,  Nobuhiko Noto

发明人： Masahiro Kato ,  Satoshi Oka ,  Norihiro Kobayashi ,  Tohru Ishizuka ,  Nobuhiko Noto

IPC分类号： H01L21/70 ,  H01L21/02 ,  H01L21/762 ,  H01L29/786

CPC分类号： H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/76254 ,  H01L29/78603

摘要： A silicon epitaxial wafer having a silicon epitaxial layer grown by vapor phase epitaxy on a main surface of a silicon single crystal substrate, wherein the main surface of the silicon single crystal substrate is tilted with respect to a [100] axis at an angle θ in a [011] direction or a [0-1-1] direction from a (100) plane and at an angle φ in a [01-1] direction or a [0-11] direction from the (100) plane, the angle θ and the angle φ are less than ten minutes, and a dopant concentration of the silicon epitaxial layer is equal to or more than 1×1019/cm3. Even when an epitaxial layer having a dopant concentration of 1×1019/cm3 or more is formed on the main surface of the silicon single crystal substrate, stripe-shaped surface irregularities on the epitaxial layer are inhibited.

摘要翻译： 一种硅外延片，其具有在硅单晶衬底的主表面上通过气相外延生长的硅外延层，其中所述硅单晶衬底的主表面相对于[100]轴以角度倾斜; 在（011）方向或[0-1-1]方向上，以（100） 在（100）平面的[01-1]方向或[0-11]方向上，角度＆amp; 和角度＆phgr 小于10分钟，硅外延层的掺杂浓度等于或大于1×1019 / cm3。 即使在硅单晶衬底的主表面上形成掺杂浓度为1×1019 / cm3以上的外延层，也抑制了外延层上的条状表面凹凸。

公开(公告)号：US08097523B2

公开(公告)日：2012-01-17

申请号：US12866271

申请日：2009-02-17

申请人： Norihiro Kobayashi ,  Tohru Ishizuka ,  Hiroji Aga ,  Nobuhiko Noto

发明人： Norihiro Kobayashi ,  Tohru Ishizuka ,  Hiroji Aga ,  Nobuhiko Noto

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/76254

摘要： A method for manufacturing a bonded wafer, including at least implanting at least one type of gas ion selected from a hydrogen ion and a rare gas ion from a surface of a bond wafer to form an ion-implanted layer in the wafer, bonding an ion-implanted surface of the bond wafer to a surface of a base wafer directly or through an insulator film, and then delaminating the bond wafer at the ion-implanted layer to fabricate a bonded wafer. A plasma treatment is applied to a bonding surface of one of the bond wafer and the base wafer to grow an oxide film, etching the grown oxide film is carried out, and bonding to the other wafer is performed. The method enables preventing defects by reducing particles on the bonding surface and performing strong bonding when effecting bonding directly or through the insulator film.

摘要翻译： 一种用于制造接合晶片的方法，包括至少从接合晶片的表面注入选自氢离子和稀有气体离子的至少一种气体离子，以在晶片中形成离子注入层，将离子 将接合晶片的植入表面直接或通过绝缘体膜的基底晶片的表面，然后在离子注入层分层接合晶片以制造接合晶片。 将等离子体处理施加到接合晶片和基底晶片之一的接合表面以生长氧化膜，进行蚀刻生长的氧化物膜，并且进行与另一晶片的接合。 该方法通过在直接或通过绝缘膜进行接合的同时还原接合表面上的颗粒并进行强结合来防止缺陷。

公开(公告)号：US07861421B2

公开(公告)日：2011-01-04

申请号：US12452070

申请日：2008-07-03

申请人： Norihiro Kobayashi ,  Tohru Ishizuka ,  Nobuhiko Noto

发明人： Norihiro Kobayashi ,  Tohru Ishizuka ,  Nobuhiko Noto

IPC分类号： G01B5/24 ,  G01B7/30

CPC分类号： H01L21/76251 ,  H01L22/12 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method for measuring a rotation angle of a bonded wafer, wherein a base wafer and a bond wafer each having a notch indicative of a crystal orientation formed at an outer edge thereof are bonded to each other at a desired rotation angle by utilizing the notches, a profile of the bond wafer having a reduced film thickness is observed with respect to a bonded wafer manufactured by reducing a film thickness of the bond wafer, a positional direction of the notch of the bond wafer seen from a center of the bonded wafer is calculated by utilizing the profile, an angle formed between the calculated positional direction of the notch of the bond wafer and a positional direction of the notch of the base wafer is calculated, and a rotation angle of the base wafer and the bond wafer is measured. As a result, the method for measuring a rotation angle of a bonded wafer that enables accurately and easily measuring the rotation angle of the notches of the base wafer and the bond wafer in a bonded wafer manufacturing line can be provided.

摘要翻译： 本发明提供了一种用于测量接合晶片的旋转角度的方法，其中每个具有指示在其外边缘处形成的晶体取向的切口的基底晶片和接合晶片以期望的旋转角度彼此接合， 利用缺口，观察到相对于通过降低接合晶片的膜厚而制造的接合晶片，从接合晶片的中心观察到的接合晶片的凹口的位置方向，观察到具有减小的膜厚度的接合晶片的轮廓 通过利用轮廓来计算贴合晶片，计算出计算的接合晶片的凹口的位置方向与基底晶片的凹口的位置方向之间形成的角度，以及基底晶片和接合晶片的旋转角度 被测量。 结果，可以提供用于测量接合晶片的旋转角度的方法，其能够准确且容易地测量接合晶片制造线中的基底晶片和接合晶片的切口的旋转角度。

公开(公告)号：US20100314722A1

公开(公告)日：2010-12-16

申请号：US12867922

申请日：2009-02-19

申请人： Tohru Ishizuka ,  Nobuhiko Noto ,  Norihiro Kobayashi ,  Masatake Nakano

发明人： Tohru Ishizuka ,  Nobuhiko Noto ,  Norihiro Kobayashi ,  Masatake Nakano

IPC分类号： H01L29/04 ,  H01L21/762

CPC分类号： H01L21/76254 ,  H01L29/045 ,  H01L29/78603

摘要： The present invention is an SOI wafer comprising at least: an SOI layer; a silicon oxide film; and a base wafer, wherein the SOI layer has a plane orientation of (100), and the base wafer has a resistivity of 100 Ω·cm or more and a plane orientation different from (100). As a result, there is provided the SOI wafer and the manufacturing method thereof that have no complicated manufacturing step, defects on a bonding interface which are not practically a problem in number and a high interface state density (Dit) for trapping carriers on an interface of a BOX layer and the base wafer.

摘要翻译： 本发明是至少包括SOI层的SOI晶片; 氧化硅膜; 以及基底晶片，其中所述SOI层具有（100）的平面取向，并且所述基底晶片的电阻率为100Ω·cm·cm以上且平面取向不同于（100）。 结果，提供了没有复杂的制造步骤的SOI晶片及其制造方法，接合界面上的缺陷在数量上几乎不成问题，并且用于在接口上捕获载体的高界面态密度（Dit） 的BOX层和基底晶片。