公开(公告)号：US5799288A

公开(公告)日：1998-08-25

申请号：US672052

申请日：1996-06-26

申请人： Takao Tanaka ,  Masanori Mukai ,  Takeshi Nagaoka ,  Kazuo Nakamura ,  Takaaki Hirooka ,  Takuji Shiota ,  Yoshihiro Kakiuchi ,  Ryoichi Tabei ,  Kouichi Matsuo

发明人： Takao Tanaka ,  Masanori Mukai ,  Takeshi Nagaoka ,  Kazuo Nakamura ,  Takaaki Hirooka ,  Takuji Shiota ,  Yoshihiro Kakiuchi ,  Ryoichi Tabei ,  Kouichi Matsuo

IPC分类号： G07D9/00 ,  G06Q10/04 ,  G06Q20/18 ,  G06Q40/00 ,  G06Q40/02 ,  G06Q50/00 ,  G07D11/00 ,  G07F19/00

CPC分类号： G07F19/211 ,  G06Q20/108 ,  G06Q20/1085 ,  G07D11/0054 ,  G07D11/0072 ,  G07D11/0075

摘要： The invention provides a remaining money management system which can predict and manage a demanded cash amount for an ATM. The remaining money management system includes one or more automatic cash transaction apparatus, and a remaining money management apparatus which manages remaining money amounts based on transaction data from the automatic cash transaction apparatus. The remaining money management apparatus includes a storage section for cumulatively storing transaction data from the automatic cash transaction apparatus, and a prediction section for calculating and predicting demanded cash amounts within a designated time for the automatic cash transaction apparatus based on transaction data in the past accumulated in the storage section. The remaining money amount management system can be applied to an apparatus for managing ATMs installed in monetary facilities such as banks.

摘要翻译： 本发明提供了可以预测和管理ATM的所需现金金额的剩余货币管理系统。 剩余的货币管理系统包括一个或多个自动现金交易装置，以及基于来自自动现金交易装置的交易数据管理剩余货币金额的剩余货币管理装置。 剩余货币管理装置包括：用于累积存储来自自动现金交易装置的交易数据的存储部分;以及预测部分，用于根据过去累积的交易数据，计算和预测在自动现金交易装置的指定时间内的所需现金金额 在存储部分。 剩余的金额管理系统可以应用于用于管理银行等货币设施中安装的ATM的装置。

公开(公告)号：US08830144B2

公开(公告)日：2014-09-09

申请号：US12661248

申请日：2010-03-12

申请人： Kazuo Nakamura ,  Katsuhide Uchino ,  Nobutoshi Asai ,  Hiroshi Sagawa

发明人： Kazuo Nakamura ,  Katsuhide Uchino ,  Nobutoshi Asai ,  Hiroshi Sagawa

IPC分类号： G09G3/30 ,  H01L27/32 ,  H01L51/52

CPC分类号： H01L27/3269 ,  G09G3/20 ,  G09G3/3208 ,  G09G2300/0421 ,  H01L27/322 ,  H01L51/5284 ,  H01L2227/32

摘要： A display panel includes: a plurality of pixel circuits formed in a matrix on a substrate; an insulating layer covering the plurality of pixel circuits; a plurality of light emitting elements connected to the plurality of pixel circuits, and arranged in a matrix on the insulating layer; a filtering layer including a light transmitting section at least in a part of a region facing the light emitting element and a light shielding section formed in a same plane as the light transmitting section, and formed on an opposite side from the pixel circuit in relation to the light emitting element; a light reflecting section formed in a region facing the light shielding section, and between the light emitting element and the filtering layer; and a light receiving element formed in a region facing the light shielding section, and on the pixel circuit side in relation to the light emitting element.

摘要翻译： 显示面板包括：在基板上以矩阵形成的多个像素电路; 覆盖所述多个像素电路的绝缘层; 连接到所述多个像素电路的多个发光元件，并且以矩阵形式布置在所述绝缘层上; 滤光层，其至少在面向发光元件的区域的一部分中具有透光部，以及形成在与透光部相同的平面中的遮光部，并且形成在与像素电路相反的一侧 发光元件; 在与所述遮光部对置的区域中形成的光反射部以及所述发光元件与所述滤光层之间的光反射部; 以及形成在面对遮光部的区域中的光接收元件，并且在像素电路侧相对于发光元件形成。

公开(公告)号：US20130200848A1

公开(公告)日：2013-08-08

申请号：US13879580

申请日：2011-09-08

申请人： Atsushi Ozawa ,  Kazuo Nakamura ,  Shin Hotta ,  Kentaro Marutani ,  Shinichi Uesaka

发明人： Atsushi Ozawa ,  Kazuo Nakamura ,  Shin Hotta ,  Kentaro Marutani ,  Shinichi Uesaka

IPC分类号： H02J7/00

CPC分类号： H02J7/0029 ,  B60L11/1855 ,  B60L2200/26 ,  H01M10/441 ,  H02J7/0019 ,  H02J7/0024 ,  H02J7/045 ,  Y02T10/7005 ,  Y02T10/705

摘要： Provided is a method for charging/discharging a battery pack having an auxiliary charging/discharging device and a battery assembly in which a plurality of secondary battery cell parallel modules, each of which includes a plurality of fasecondary battery cells connected in parallel, are connected in series, the method including, when there is no abnormality in the secondary battery cells during charging/discharging, connecting the auxiliary charging/discharging device in parallel to any of the secondary battery cell parallel modules, and when there is an abnormality in any of the secondary battery cells during charging/discharging, releasing connection to the secondary battery cell at which the abnormality has arisen in the secondary battery cell parallel module including the secondary battery cell at which the abnormality has arisen, and connecting the auxiliary charging/discharging device in parallel to the secondary battery cell parallel module including the secondary battery cell at which the abnormality has arisen.

摘要翻译： 本发明提供一种具有辅助充电/放电装置和电池组件的电池组的充电/放电方法，其中包括并联连接的多个第二电池单元的多个二次电池单元并联模块连接在 该方法包括当在充电/放电期间二次电池单元中没有异常时，将辅助充电/放电装置与任何二次电池单元并联模块并联连接，并且当任何一个 在充放电期间的二次电池单元，在包括产生异常的二次电池的二次电池单元并联模块中发生异常的二次电池单元的连接，并且并联连接辅助充电/放电装置 涉及包括二次电池单元a的二次电池单元并联模块 这产生了异常。

公开(公告)号：US08330682B2

公开(公告)日：2012-12-11

申请号：US12543558

申请日：2009-08-19

申请人： Kazuo Nakamura ,  Katsuhide Uchino

发明人： Kazuo Nakamura ,  Katsuhide Uchino

IPC分类号： G09G3/30

CPC分类号： G09G3/3233 ,  G09G2320/0233 ,  G09G2320/0285 ,  G09G2320/041 ,  G09G2320/043 ,  G09G2320/0693

摘要： A display apparatus includes: a plurality of pixel circuits arrayed in a matrix fashion; a light emitting circuit provided to each pixel circuit and emitting light correspondingly to a drive current; and a detection circuit provided to a predetermined pixel circuit and outputting a signal according to a temperature that varies with luminance of the light emitting circuit.

摘要翻译： 显示装置包括：以矩阵方式排列的多个像素电路; 提供给每个像素电路并且对应于驱动电流发光的发光电路; 以及检测电路，其被提供给预定的像素电路，并且根据随着发光电路的亮度而变化的温度输出信号。

公开(公告)号：US08237691B2

公开(公告)日：2012-08-07

申请号：US12167263

申请日：2008-07-03

申请人： Kazuo Nakamura

发明人： Kazuo Nakamura

IPC分类号： G06F3/038

CPC分类号： G09G3/3688 ,  G09G3/2011 ,  G09G2310/027

摘要： A display driver circuit of a display device includes: a first DA converter for converting a digital data to a gray-scale potential within a first potential range; and a second DA converter for converting a digital data to a gray-scale potential within a second potential range lower than the first potential range. The first DA converter includes a first transistor of a first conductivity type outputting a gray-scale potential not less than the common potential. The second DA converter includes: a second transistor of the first conductivity type outputting a gray-scale potential not less than the common potential; and a third transistor of a second conductivity type outputting a gray-scale potential not more than the common potential. A substrate potential applied to a back gate of the second transistor is lower than a substrate potential applied to a back gate of the first transistor.

摘要翻译： 显示装置的显示驱动电路包括：第一DA转换器，用于将数字数据转换为第一电位范围内的灰度级电位; 以及第二DA转换器，用于在低于第一电位范围的第二电位范围内将数字数据转换为灰度级电位。 第一DA转换器包括输出不小于公共电位的灰度电位的第一导电类型的第一晶体管。 第二DA转换器包括：第一导电类型的第二晶体管输出不小于公共电位的灰度电位; 以及第二导电类型的第三晶体管，其输出不大于所述公共电位的灰度电势。 施加到第二晶体管的背栅极的衬底电位低于施加到第一晶体管的背栅极的衬底电位。

公开(公告)号：US08223107B2

公开(公告)日：2012-07-17

申请号：US11987860

申请日：2007-12-05

申请人： Kazuo Nakamura

发明人： Kazuo Nakamura

IPC分类号： G09G3/36

CPC分类号： G11C19/28 ,  G11C19/00

摘要： A data driver circuit includes a clock control circuit configured to generate a shift clock signal in synchronization to a clock signal; a shift register circuit having flip-flops in cascade-connection and configured to shift a pulse signal in synchronization with the shift clock signal, and a control circuit configured to receive a display data in response to the shifted pulse signal from the shift register circuit and to drive data lines of a display section based on display data to display the display data on the display section. The flip-flops are grouped in units of N (N is an integer of 2 or more) flip-flops into M (M is an integer of 2 or more) partial shift registers, and the shift register circuit is reset in units of partial shift registers.

摘要翻译： 数据驱动电路包括：时钟控制电路，被配置为与时钟信号同步地生成移位时钟信号; 移位寄存器电路，其具有级联连接的触发器并且被配置为与所述移位时钟信号同步地移位脉冲信号;以及控制电路，被配置为响应于来自所述移位寄存器电路的移位的脉冲信号而接收显示数据，以及 基于显示数据驱动显示部分的数据线，以在显示部分上显示显示数据。 触发器以N（N为2以上的整数）触发器为单位分组为M（M为2以上的整数）部分移位寄存器，移位寄存器电路以部分 移位寄存器

公开(公告)号：US20100285387A1

公开(公告)日：2010-11-11

申请号：US12735270

申请日：2008-12-24

申请人： Kenjiro Fujita ,  Kazuo Nakamura ,  Yoshio Matsuzaki ,  Makoto Koi

发明人： Kenjiro Fujita ,  Kazuo Nakamura ,  Yoshio Matsuzaki ,  Makoto Koi

IPC分类号： H01M8/24

CPC分类号： H01M8/1213 ,  H01M8/0204 ,  H01M8/1286 ,  H01M8/2425 ,  H01M8/2428

摘要： There is obtained a segmented-in-series solid oxide fuel cell provided with a current turnaround structure and containing a porous electrically insulating substrate having a fuel flow path extending from a fuel feed port to a fuel discharge port, provided therein, and a pair of the top and back surfaces, in parallel with the fuel flow path, together with a pair of side-faces of the porous electrically insulating substrate, in the transverse direction thereof, provided on the exterior thereof, wherein solid oxide fuel cells made up by sequentially stacking an interconnector adjacent to a fuel electrode layer, the fuel electrode layer, an electrolyte layer, and an air electrode layer, and an interconnector adjacent to the air electrode layer in that order so as to be in parallel with the fuel flow path are disposed at intervals on the pair of the top and back surfaces, respectively.

摘要翻译： 获得具有电流翻转结构的分段式串联固体氧化物燃料电池，并且包含具有从设置在其中的燃料供给口延伸到燃料排出口的燃料流路的多孔电绝缘基板和一对 与燃料流动路径平行的顶表面和后表面与多孔电绝缘基板的横向方向上的一对侧面一起设置在其外部，其中固体氧化物燃料电池依次构成 布置与燃料电极层相邻的互连器，燃料电极层，电解质层和空气电极层以及与空气电极层相邻的与金属流路平行的顺序的互连器 分别在一对顶表面和后表面上的间隔。

公开(公告)号：US07777739B2

公开(公告)日：2010-08-17

申请号：US11339552

申请日：2006-01-26

申请人： Takashi Nakamura ,  Hirotaka Hayashi ,  Hisao Fujiwara ,  Masao Karube ,  Kazuo Nakamura ,  Masakatsu Kitani

发明人： Takashi Nakamura ,  Hirotaka Hayashi ,  Hisao Fujiwara ,  Masao Karube ,  Kazuo Nakamura ,  Masakatsu Kitani

IPC分类号： G09G5/00

CPC分类号： G09G3/2011 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2310/0248 ,  G09G2310/027 ,  G09G2310/0291 ,  G09G2310/0297 ,  G09G2320/0233 ,  G09G2330/02 ,  G09G2330/021 ,  H03M1/804

摘要： A signal line drive circuit according to the present invention has: a latch circuit which latches digital pixel data; a D/A converter which converts a latch output from the latch circuit into an analog video signal; an AMP which amplifies the analog video signal converted by the D/A converter; and a signal selection circuit which selects a signal line to which the analog video signal amplified by the AMP is supplied. The AMP has: an odd number of inverters which are cascade-connected; capacitor elements which are respectively connected between stages of the inverters and between an input terminal of the inverter on a first stage and an output terminal of the inverter on a last stage; a first power supply line which supplies a power supply voltage to the inverter on the first stage; and a second power supply line which supplies a power supply voltage to inverters other than the inverter on the first stage. The accuracy of the AMP can be improved by separating the power supply line for only the inverter on the first stage.

摘要翻译： 根据本发明的信号线驱动电路具有锁存数字像素数据的锁存电路; D / A转换器，其将来自锁存电路的锁存器输出转换为模拟视频信号; 放大由D / A转换器转换的模拟视频信号的AMP; 以及信号选择电路，其选择供给由AMP放大的模拟视频信号的信号线。 AMP具有：奇数级逆变器级联; 电容器元件分别连接在反相器的级之间，在第一级的反相器的输入端和最后级的反相器的输出端之间; 在第一级上向逆变器供给电源电压的第一电源线; 以及第二电源线，其向第一级上的逆变器的逆变器供给电源电压。 通过在第一级分离仅逆变器的电源线，可以提高AMP的精度。

公开(公告)号：US07477225B2

公开(公告)日：2009-01-13

申请号：US11106710

申请日：2005-04-15

申请人： Kazuo Nakamura

发明人： Kazuo Nakamura

IPC分类号： G09G3/36

CPC分类号： G09G3/3685 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/021 ,  G09G2330/06 ,  G11C19/00

摘要： Current consumption in a start signal outputting circuit, and that in a clock signal conductor thereto, or the EMI is to be suppressed. An output from the last stage flipflop of a shift register, having multiple stages of flipflops, is supplied to a start signal outputting circuit. An output of the start signal outputting circuit is delivered as a start signal, while being delivered to a start signal output detection circuit. A detection signal from a start signal output detection circuit and an output of a non-last stage flipflop of the shift register are supplied to a clock stop circuit. Clock signals cease to be supplied by the clock stop circuit during a time period as from inputting of the detection signal until inputting of the output of the non-last stage flip-flop.

摘要翻译： 启动信号输出电路中的电流消耗以及时钟信号导体中的电流消耗或EMI被抑制。 具有多级触发器的移位寄存器的最后级触发器的输出被提供给起始信号输出电路。 开始信号输出电路的输出作为起始信号传送，同时被传送到起始信号输出检测电路。 来自起始信号输出检测电路的检测信号和移位寄存器的非最后级触发器的输出被提供给时钟停止电路。 在从输入检测信号直到输入非最后级触发器的输入的时间段期间，时钟停止电路不再提供时钟信号。

公开(公告)号：US20080265783A1

公开(公告)日：2008-10-30

申请号：US12075232

申请日：2008-03-10

申请人： Kazuo Nakamura

发明人： Kazuo Nakamura

IPC分类号： G09G3/00 ,  H01J9/02

CPC分类号： G09G3/3208 ,  G09G2300/0426 ,  G09G2330/02 ,  H01L27/3279

摘要： Disclosed is a display panel having a display area with a matrix array of display pixels. The display panel includes an electrode arranged so as to cover the whole of the display area, and a common electrode electrically connected to the electrode. The common electrode is frame-shaped and is arranged along the periphery of the display area. The common electrode has a notch that is opposed to a power supply lead pattern to which a potential different from that applied to the common electrode is applied.

摘要翻译： 公开了一种显示面板，其具有显示区域和显示像素的矩阵阵列。 显示面板包括布置成覆盖整个显示区域的电极和与电极电连接的公共电极。 公共电极是框形的，并且沿着显示区域的周边布置。 公共电极具有与施加与施加到公共电极的电位不同的电位的电源引线图案相对的凹口。