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    SEMICONDUCTOR MEMORY DEVICE WHICH CAN BE SIMULTANEOUSLY TESTED EVEN WHEN THE NUMBER OF SEMICONDUCTOR MEMORY DEVICES IS LARGE AND SEMICONDUCTOR WAFER ON WHICH THE SEMICONDUCTOR MEMORY DEVICES ARE FORMED
    1.
    发明授权
    SEMICONDUCTOR MEMORY DEVICE WHICH CAN BE SIMULTANEOUSLY TESTED EVEN WHEN THE NUMBER OF SEMICONDUCTOR MEMORY DEVICES IS LARGE AND SEMICONDUCTOR WAFER ON WHICH THE SEMICONDUCTOR MEMORY DEVICES ARE FORMED 失效
    半导体存储器件的半导体存储器件，即使半导体存储器件的数量大于半导体存储器件形成的半导体器件，也可以同时测试

    公开(公告)号：US06473345B2

    公开(公告)日：2002-10-29

    申请号：US09909786

    申请日：2001-07-23

    申请人： Takashi Hayasaka ,  Yoshikazu Miyawaki ,  Atsushi Ohba

    发明人： Takashi Hayasaka ,  Yoshikazu Miyawaki ,  Atsushi Ohba

    IPC分类号： G11C700

    CPC分类号： G11C29/48 ,  G11C29/006

    摘要： At the time of writing data, a tester outputs a chip enable signal /CE of the L level and selection signals of the L level to simultaneously make semiconductor memory devices active. At the time of reading data, the tester outputs the chip enable signal of the L level to the semiconductor memory devices, and selectively switches the logic level of a selection signal to be outputted to some semiconductor memory devices and that of the selection signal to be outputted to the other semiconductor memory devices to the L level. In such a manner, a number of semiconductor memory devices can be tested without increasing the number of pins of the tester.

    摘要翻译： 在写入数据时，测试仪输出L电平的芯片使能信号/ CE和L电平的选择信号，以同时使半导体存储器件处于活动状态。 在读取数据时，测试仪将半导体存储器件的L电平的芯片使能信号输出到选择信号的选择信号的逻辑电平，并将选择信号的逻辑电平切换到一些半导体存储器件 输出到其他半导体存储器件到L电平。 以这种方式，可以在不增加测试器的引脚数的情况下测试多个半导体存储器件。

    Static semiconductor memory device having circuitry for lowering potential of bit lines at commencement of data writing
    2.
    发明授权
    Static semiconductor memory device having circuitry for lowering potential of bit lines at commencement of data writing 失效
    具有用于在开始数据写入时降低位线的电位的电路的静态半导体存储器件

    公开(公告)号：US5544105A

    公开(公告)日：1996-08-06

    申请号：US271691

    申请日：1994-07-07

    申请人： Toshihiko Hirose ,  Shigeki Ohbayashi ,  Setsu Kondo ,  Takashi Hayasaka ,  Yoshiyuki Fujino ,  Masayuki Iketani

    发明人： Toshihiko Hirose ,  Shigeki Ohbayashi ,  Setsu Kondo ,  Takashi Hayasaka ,  Yoshiyuki Fujino ,  Masayuki Iketani

    IPC分类号： G11C11/41 ,  G11C7/14 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/417 ,  G11C11/419 ,  G11C29/00 ,  G11C7/00

    CPC分类号： G11C29/78 ,  G11C11/417 ,  G11C11/419 ,  G11C7/14 ,  G11C7/22

    摘要： A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.

    摘要翻译： 延迟电路将内部写入控制信号延迟规定时间到全局写入驱动器。 全局写入驱动器响应于从延迟电路接收的延迟的写入控制信号而使能，以根据来自输入缓冲器的内部写入数据驱动全局写入数据总线。 响应于内部写入控制信号和块选择信号来使能块写入驱动器，以响应于全局写入数据总线上的数据驱动本地写入数据总线。 写入门响应于列选择信号将位线连接到本地写数据总线。 延迟电路将块写入驱动器的输出设定为低电平达规定的周期，从而降低位线的预充电电位以减小数据写入中位线的电位振幅。 提供了一种以高速运行并具有放大的写恢复时间裕度的SRAM。 SRAM还包括用于改进操作特性和可靠性的各种布置。

    Static semiconductor memory device having circuitry for enlarging write recovery margin
    4.
    发明授权
    Static semiconductor memory device having circuitry for enlarging write recovery margin 失效
    具有放大写恢复余量的电路的静态半导体存储器件

    公开(公告)号：US5506805A

    公开(公告)日：1996-04-09

    申请号：US402212

    申请日：1995-03-10

    申请人： Toshihiko Hirose ,  Shigeki Ohbayashi ,  Setsu Kondo ,  Takashi Hayasaka ,  Yoshiyuki Fujino ,  Masayuki Iketani

    发明人： Toshihiko Hirose ,  Shigeki Ohbayashi ,  Setsu Kondo ,  Takashi Hayasaka ,  Yoshiyuki Fujino ,  Masayuki Iketani

    IPC分类号： G11C11/41 ,  G11C7/14 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/417 ,  G11C11/419 ,  G11C29/00 ,  G11C7/00

    CPC分类号： G11C29/78 ,  G11C11/417 ,  G11C11/419 ,  G11C7/14 ,  G11C7/22

    摘要： A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.

    摘要翻译： 延迟电路将内部写入控制信号延迟规定时间到全局写入驱动器。 全局写入驱动器响应于从延迟电路接收的延迟的写入控制信号而使能，以根据来自输入缓冲器的内部写入数据驱动全局写入数据总线。 响应于内部写入控制信号和块选择信号来使能块写入驱动器，以响应于全局写入数据总线上的数据驱动本地写入数据总线。 写入门响应于列选择信号将位线连接到本地写数据总线。 延迟电路将块写入驱动器的输出设定为低电平达规定的周期，从而降低位线的预充电电位以减小数据写入中位线的电位振幅。 提供了一种以高速运行并具有放大的写恢复时间裕度的SRAM。 SRAM还包括用于改善操作特性和可靠性的各种布置。

    Semiconductor integrated circuit and testing method thereof
    5.
    发明申请
    Semiconductor integrated circuit and testing method thereof 有权

    公开(公告)号：US20070198880A1

    公开(公告)日：2007-08-23

    申请号：US11785213

    申请日：2007-04-16

    申请人： Yoshio Takazawa ,  Toshio Yamada ,  Kazumasa Yanagisawa ,  Takashi Hayasaka

    发明人： Yoshio Takazawa ,  Toshio Yamada ,  Kazumasa Yanagisawa ,  Takashi Hayasaka

    IPC分类号： G11C29/00

    CPC分类号： G11C29/26 ,  G11C2029/1806 ,  G11C2029/2602 ,  G11C2029/3202

    摘要： There are provided a plurality of bridge circuits which convert the test data information from a common test bus connected to a plurality of memories of different access data widths and address decode logics to the inherent access data widths of each memory and also convert the test address information from the common test bus to the inherent bit format of each memory to supply the result to the corresponding memory. The test address information is supplied in parallel from the common test bus to a plurality of memories to realize the parallel tests. Accordingly, the test data information can be supplied in parallel to a plurality of memories of different data widths and the address scan direction in the respective memories for the test address information can be uniformed to the particular direction depending on the inherent bit format. Thereby, the memory test efficiency by the match pattern for a plurality of on-chip memories can be improved.

    Non-volatile semiconductor memory device that can be fabricated with erasure unit modified
    6.
    发明授权
    Non-volatile semiconductor memory device that can be fabricated with erasure unit modified 有权
    可以用擦除单元修改的非易失性半导体存储器件

    公开(公告)号：US06760259B1

    公开(公告)日：2004-07-06

    申请号：US10624599

    申请日：2003-07-23

    申请人： Tomoshi Futatsuya ,  Takashi Hayasaka ,  Taku Ogura

    发明人： Tomoshi Futatsuya ,  Takashi Hayasaka ,  Taku Ogura

    IPC分类号： G11C1616

    CPC分类号： G11C16/08 ,  G11C16/16 ,  G11C16/344

    摘要： Particular blocks are a boot block and parameter block having a storage capacity smaller than that of a general block. In the case where a boot block is not required, a signal BOOTE is set at an L level. In the case where a signal BLKSEL is at an H level in an erasure mode, a control unit selects four blocks aligned in a horizontal direction at the same time. The control unit also selects two blocks simultaneously in the vertical direction. As a result, the particular eight blocks are selected. The boot block and parameter block can be erased collectively as one block having a capacity similar to that of a general block. Therefore, a flash memory corresponding to the case of including a boot block and not including a boot block can be implemented simultaneously with one chip. Thus, the designing and fabrication process can be simplified.

    摘要翻译： 特定块是具有比一般块的存储容量小的存储容量的引导块和参数块。 在不需要引导块的情况下，将信号BOOTE设定为L电平。 在擦除模式中信号BLKSEL处于H电平的情况下，控制单元同时选择沿水平方向排列的四个块。 控制单元同时在垂直方向上同时选择两个块。 结果，选择特定的八个块。 引导块和参数块可以被集体地擦除为具有与一般块相同的容量的一个块。 因此，可以与一个芯片同时实现与包括引导块并且不包括引导块的情况相对应的闪速存储器。 因此，可以简化设计和制造过程。

    Static semiconductor memory device having improved characteristics
    7.
    发明授权
    Static semiconductor memory device having improved characteristics 失效
    具有改进特性的静态半导体存储器件

    公开(公告)号：US5659513A

    公开(公告)日：1997-08-19

    申请号：US526245

    申请日：1995-09-11

    申请人： Toshihiko Hirose ,  Shigeki Ohbayashi ,  Setsu Kondo ,  Takashi Hayasaka ,  Yoshiyuki Fujino ,  Masayuki Iketani

    发明人： Toshihiko Hirose ,  Shigeki Ohbayashi ,  Setsu Kondo ,  Takashi Hayasaka ,  Yoshiyuki Fujino ,  Masayuki Iketani

    IPC分类号： G11C11/41 ,  G11C7/14 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/417 ,  G11C11/419 ,  G11C29/00 ,  G05F3/24

    CPC分类号： G11C29/78 ,  G11C11/417 ,  G11C11/419 ,  G11C7/14 ,  G11C7/22

    摘要： A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.

    摘要翻译： 延迟电路将内部写入控制信号延迟规定时间到全局写入驱动器。 全局写入驱动器响应于从延迟电路接收的延迟的写入控制信号而使能，以根据来自输入缓冲器的内部写入数据驱动全局写入数据总线。 响应于内部写入控制信号和块选择信号来使能块写入驱动器，以响应于全局写入数据总线上的数据驱动本地写入数据总线。 写入门响应于列选择信号将位线连接到本地写数据总线。 延迟电路将块写入驱动器的输出设定为低电平达规定的周期，从而降低位线的预充电电位以减小数据写入中位线的电位振幅。 提供了一种以高速运行并具有放大的写恢复时间裕度的SRAM。 SRAM还包括用于改善操作特性和可靠性的各种布置。

    Optical amplification apparatus, optical communication apparatus, and optical communication method
    10.
    发明授权
    Optical amplification apparatus, optical communication apparatus, and optical communication method 有权
    光放大装置，光通信装置和光通信方法

    公开(公告)号：US08049955B2

    公开(公告)日：2011-11-01

    申请号：US12285229

    申请日：2008-09-30

    申请人： Miki Onaka ,  Yasushi Sugaya ,  Togo Fukushi ,  Masanori Kondoh ,  Kiyotoshi Noheji ,  Takashi Hayasaka

    发明人： Miki Onaka ,  Yasushi Sugaya ,  Togo Fukushi ,  Masanori Kondoh ,  Kiyotoshi Noheji ,  Takashi Hayasaka

    IPC分类号： H04B10/17 ,  H04B10/12

    CPC分类号： H04B10/2931 ,  H04B10/07953

    摘要： A Raman amplifier inputs pump light into an optical fiber (transmission path) through which an optical signal passes, to amplify the optical signal. An optical receiving unit is provided downstream of the Raman amplifier and monitors the power of the optical signal amplified by the Raman amplifier. A calculating unit determines Raman amplification gain based on the power of the optical signal monitored by the optical receiving unit, and calculates the power of a noise component included in the optical signal based on the gain. The calculating unit, in real-time, calculates the power, which varies in complicated manners depending on conditions, and outputs information concerning to the power to another apparatus at a frequency on the order of milliseconds.

    摘要翻译： 拉曼放大器将泵浦光输入到光信号通过的光纤（传输路径）中，以放大光信号。 光接收单元设置在拉曼放大器的下游，并监视由拉曼放大器放大的光信号的功率。 计算单元基于由光接收单元监视的光信号的功率来确定拉曼放大增益，并且基于增益计算包括在光信号中的噪声分量的功率。 计算单元实时地计算根据条件以复杂的方式变化的功率，并且以与毫秒数量级的频率将关于功率的信息输出到另一设备。