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公开(公告)号：US20070198880A1
公开(公告)日：2007-08-23
申请号：US11785213
申请日：2007-04-16
IPC分类号： G11C29/00
CPC分类号： G11C29/26 , G11C2029/1806 , G11C2029/2602 , G11C2029/3202
摘要： There are provided a plurality of bridge circuits which convert the test data information from a common test bus connected to a plurality of memories of different access data widths and address decode logics to the inherent access data widths of each memory and also convert the test address information from the common test bus to the inherent bit format of each memory to supply the result to the corresponding memory. The test address information is supplied in parallel from the common test bus to a plurality of memories to realize the parallel tests. Accordingly, the test data information can be supplied in parallel to a plurality of memories of different data widths and the address scan direction in the respective memories for the test address information can be uniformed to the particular direction depending on the inherent bit format. Thereby, the memory test efficiency by the match pattern for a plurality of on-chip memories can be improved.
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公开(公告)号：US07426663B2
公开(公告)日：2008-09-16
申请号：US11785213
申请日：2007-04-16
CPC分类号： G11C29/26 , G11C2029/1806 , G11C2029/2602 , G11C2029/3202
摘要： There are provided a plurality of bridge circuits which convert the test data information from a common test bus connected to a plurality of memories of different access data widths and address decode logics to the inherent access data widths of each memory and also convert the test address information from the common test bus to the inherent bit format of each memory to supply the result to the corresponding memory. The test address information is supplied in parallel from the common test bus to a plurality of memories to realize the parallel tests. Accordingly, the test data information can be supplied in parallel to a plurality of memories of different data widths and the address scan direction in the respective memories for the test address information can be uniformed to the particular direction depending on the inherent bit format. Thereby, the memory test efficiency by the match pattern for a plurality of on-chip memories can be improved.
摘要翻译： 提供了多个桥接电路，其将来自连接到不同访问数据宽度的多个存储器的公共测试总线的测试数据信息和地址解码逻辑转换为每个存储器的固有访问数据宽度，并且还将测试地址信息 从公共测试总线到每个存储器的固有位格式，将结果提供给相应的存储器。 测试地址信息从公共测试总线并行提供给多个存储器以实现并行测试。 因此，测试数据信息可以并行地提供给不同数据宽度的多个存储器，并且用于测试地址信息的各个存储器中的地址扫描方向可以根据固有位格式被均匀化到特定方向。 因此，可以提高通过用于多个片上存储器的匹配模式的存储器测试效率。
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公开(公告)号：US07222272B2
公开(公告)日：2007-05-22
申请号：US10430319
申请日：2003-05-07
CPC分类号： G11C29/26 , G11C2029/1806 , G11C2029/2602 , G11C2029/3202
摘要： There are provided a plurality of bridge circuits which convert the test data information from a common test bus connected to a plurality of memories of different access data widths and address decode logics to the inherent access data widths of each memory and also convert the test address information from the common test bus to the inherent bit format of each memory to supply the result to the corresponding memory. The test address information is supplied in parallel from the common test bus to a plurality of memories to realize the parallel tests. Accordingly, the test data information can be supplied in parallel to a plurality of memories of different data widths and the address scan direction in the respective memories for the test address information can be uniformed to the particular direction depending on the inherent bit format. Thereby, the memory test efficiency by the match pattern for a plurality of on-chip memories can be improved.
摘要翻译： 提供了多个桥接电路，其将来自连接到不同访问数据宽度的多个存储器的公共测试总线的测试数据信息和地址解码逻辑转换为每个存储器的固有访问数据宽度，并且还将测试地址信息 从公共测试总线到每个存储器的固有位格式，将结果提供给相应的存储器。 测试地址信息从公共测试总线并行提供给多个存储器以实现并行测试。 因此，测试数据信息可以并行地提供给不同数据宽度的多个存储器，并且用于测试地址信息的各个存储器中的地址扫描方向可以根据固有位格式被均匀化到特定方向。 因此，可以提高通过用于多个片上存储器的匹配模式的存储器测试效率。
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4.发明授权公开(公告)号：US06897496B2
公开(公告)日：2005-05-24
申请号：US09982839
申请日：2001-10-22
IPC分类号： H01L21/3205 , G11C5/02 , G11C5/06 , H01L21/82 , H01L21/822 , H01L23/52 , H01L27/04 , H01L29/73
摘要： Outside-cell wiring that extends the upper part of a macro cell to the direction of X axis is composed of the wiring layer of the upper layer than a terminal for a signal of the macro cell and this terminal is formed to extend in the direction of Y axis (direction that intersects the direction of X axis) so that the outside-cell wiring can be secured for a plurality of wiring channels. The macro cell and the outside-cell wiring are connected via this signal terminal.
摘要翻译： 将宏单元的上部延伸到X轴方向的外电池布线由与宏单元的信号的端子相比上层的布线层构成，该端子形成为沿着宏单元的方向延伸 Y轴（与X轴方向相交的方向），从而可以确保多个布线通道的外部单元布线。 宏单元和外部单元布线通过该信号端子连接。
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公开(公告)号：US08829968B2
公开(公告)日：2014-09-09
申请号：US12555143
申请日：2009-09-08
IPC分类号： H03L5/00
CPC分类号： H03K19/0016 , H01L23/5286 , H01L27/0207 , H01L27/092 , H01L27/0928 , H01L27/11898 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.
摘要翻译： 具有第一电路块BLK1，第二电路块DRV1和用于将第一电路块连接到第二电路块的转换电路MIO1的半导体集成电路器件。 第一电路块包括用于施加电源电压的第一模式和用于关断电源电压的第二模式。 转换电路具有将第二电路块的输入节点的电位维持在操作电位的功能，从而当第一电路块处于第二模式时抑制穿透电流流动。 转换电路（MIO1〜MIO4）通常用于连接电路块。
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公开(公告)号：US08264870B2
公开(公告)日：2012-09-11
申请号：US12891208
申请日：2010-09-27
CPC分类号： G11C11/417 , G11C5/14 , G11C5/148
摘要： When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.
摘要翻译： 当降低构成晶体管的阈值电压以便在低电压下操作SRAM电路时，存在晶体管的漏电流增加的问题，结果是当SRAM电路不工作时的功耗 同时存储数据增加。 因此，提供了通过控制存储单元中的驱动器MOS晶体管的源极线ssl的电位来减小SRAM存储单元MC中的MOS晶体管的漏电流的技术。
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公开(公告)号：US08084869B2
公开(公告)日：2011-12-27
申请号：US12478837
申请日：2009-06-05
IPC分类号： H01L23/29
CPC分类号： H01L23/49838 , H01L21/563 , H01L24/13 , H01L24/16 , H01L24/48 , H01L24/81 , H01L25/0657 , H01L25/105 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/056 , H01L2224/13144 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48105 , H01L2224/48227 , H01L2224/48229 , H01L2224/73204 , H01L2224/73253 , H01L2224/81203 , H01L2224/81801 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H05K1/112 , H05K3/4652 , H05K2201/09227 , H05K2201/099 , H05K2201/10734 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A technique permitting the reduction in size of a semiconductor device is provided. In a BGA type semiconductor device with a semiconductor chip flip-chip-bonded onto a wiring substrate, bump electrodes of the semiconductor chip are coupled to lands formed at an upper surface of the wiring substrate. The lands at the upper surface of the wiring substrate are coupled electrically to solder balls formed on a lower surface of the wiring substrate. Therefore, the lands include first type lands with lead-out lines coupled thereto and second type lands with lead-out lines not coupled thereto but with vias formed just thereunder. The lands are arrayed in six or more rows at equal pitches in an advancing direction of the rows. However, a row-to-row pitch is not made an equal pitch. In land rows which are likely to cause a short-circuit, the pitch between adjacent rows is made large, while in land rows which are difficult to cause a short-circuit, the pitch between adjacent rows is made small. By so doing, both prevention of a short-circuit and improvement of the layout density of lands are attained at a time.
摘要翻译： 提供了允许半导体器件的尺寸减小的技术。 在具有倒装芯片接合在布线基板上的半导体芯片的BGA型半导体器件中，半导体芯片的突起电极被耦合到在布线基板的上表面上形成的焊盘。 布线基板的上表面的焊盘电连接到形成在布线基板的下表面上的焊球。 因此，焊盘包括具有与其耦合的引出线的第一类型的焊盘和没有耦合到其上的导出线，但是具有刚好形成的通孔的第二类型的焊盘。 焊盘沿着行的前进方向以等间距排列成六行或更多行。 然而，行到行间距不是相等的音高。 在可能导致短路的陆地列中，相邻行之间的间距变大，而在难以引起短路的陆地行中，相邻行之间的间距变小。 通过这样做，一次可以实现防止短路的改善和布局密度的提高。
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公开(公告)号：US07855593B2
公开(公告)日：2010-12-21
申请号：US12497982
申请日：2009-07-06
CPC分类号： G11C5/147
摘要： A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided. The semiconductor integrated circuit device has first through third circuit blocks, and is placed in a first power supply state in which the operation of internal circuits in the first circuit block is guaranteed in accordance with an instruction from the third circuit block or a second power supply state in which the operation of the internal circuits is not guaranteed. The second circuit block has an input unit which receives signals supplied from the first circuit block, and the input unit of the second circuit block has an input circuit which, in accordance with a control signal sent from said third circuit block to said second circuit block, causes a specific signal level to be maintained in compliance with the operating voltage of the second circuit block irrespective of the signal supplied from the first circuit block when the third circuit block instructs the second power supply state to the first circuit block.
摘要翻译： 提供一种在实现多功能化和省电的同时提高设计效率的半导体集成电路装置。 半导体集成电路装置具有第一至第三电路块，并且被置于第一电源状态，其中根据来自第三电路块或第二电源的指令保证第一电路块中的内部电路的操作 不能保证内部电路的运行状态。 第二电路块具有接收从第一电路块提供的信号的输入单元，并且第二电路块的输入单元具有输入电路，该输入电路根据从所述第三电路块发送到所述第二电路块的控制信号 当第三电路块向第一电路块指示第二电源状态时，使得与第二电路块的工作电压保持一定的特定信号电平，而与第一电路块所提供的信号无关。
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公开(公告)号：US07821814B2
公开(公告)日：2010-10-26
申请号：US12222753
申请日：2008-08-15
CPC分类号： G11C11/417 , G11C5/14 , G11C5/148
摘要： When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.
摘要翻译： 当降低构成晶体管的阈值电压以便在低电压下操作SRAM电路时，存在晶体管的漏电流增加的问题，结果是当SRAM电路不工作时的功耗 同时存储数据增加。 因此，提供了通过控制存储单元中的驱动器MOS晶体管的源极线ssl的电位来减小SRAM存储单元MC中的MOS晶体管的漏电流的技术。
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公开(公告)号：US07786585B2
公开(公告)日：2010-08-31
申请号：US12188591
申请日：2008-08-08
申请人： Takako Funakoshi , Eiichi Murakami , Kazumasa Yanagisawa , Kan Takeuchi , Hideo Aoki , Hizuru Yamaguchi , Takayuki Oshima , Kazuyuki Tsunokuni , Kousuke Okuyama
发明人： Takako Funakoshi , Eiichi Murakami , Kazumasa Yanagisawa , Kan Takeuchi , Hideo Aoki , Hizuru Yamaguchi , Takayuki Oshima , Kazuyuki Tsunokuni , Kousuke Okuyama
CPC分类号： H01L23/53238 , H01L21/823871 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.
摘要翻译： 在具有多层埋地布线的半导体集成电路装置中，旨在防止在其底部连接到埋地布线的插头与埋地布线之间的界面处的应力迁移引起的不连续性的发生。 例如，在第一Cu布线的宽度不小于约0.9μm且小于约1.44μm的情况下，并且第二Cu布线的宽度和塞子的直径为约0.18μm的情况下，存在 布置两个或更多个将第一布线和第二铜布线彼此电连接的插头。
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