公开(公告)号：US20120243326A1

公开(公告)日：2012-09-27

申请号：US13403294

申请日：2012-02-23

Applicant: Takashi MAEDA

Inventor： Takashi MAEDA

IPC: G11C16/26

CPC classification number: G11C16/26

Abstract: According to one embodiment, a device includes transistors each with a path connected to a bit line, and circuits each includes a switch, the circuit being connected to the bit line. The device includes a amplifier connected to the transistor and to the circuit, and a latch connected to the amplifier to hold first data before read is carried out on a cell and to hold second data if a current equal to or a larger than a predetermined value flows via the bit line. In the device, the switch is turned on or off depending on data held in another latch located adjacently in a direction of the word lines, to control a connection between the bit line and connected to another bit line the amplifier via the circuit.

Abstract translation: 根据一个实施例，一种器件包括各自具有连接到位线的路径的晶体管，并且电路各自包括开关，该电路连接到位线。 该装置包括连接到晶体管和电路的放大器，以及连接到放大器的锁存器，用于在小区上执行读取之前保存第一数据，并且如果电流等于或大于预定值，则保持第二数据 通过位线流动。 在该装置中，取决于保持在与字线方向相邻的另一个锁存器中的数据，开关被接通或断开，以控制位线之间的连接，并通过该电路连接到放大器的另一位线。

公开(公告)号：US20120081761A1

公开(公告)日：2012-04-05

申请号：US13073787

申请日：2011-03-28

Applicant: Naoyuki NAKAMURA ,  Takashi MAEDA

Inventor： Naoyuki NAKAMURA ,  Takashi MAEDA

IPC: H04N1/04

CPC classification number: H04N1/00803 ,  H04N1/00962 ,  H04N2201/0094 ,  H04N2201/0098

Abstract: An image reader includes a reading unit that is configured to read an image on a document sheet to generate read data, a counting unit that is configured to count a number of pixels of the read data having more than a predetermined gray level, a determining unit that determines that the document sheet is blank when the number of pixels counted by the counting unit is not exceeding a threshold value, a display unit that is configured to display the number of pixels counted by the counting unit and the threshold value when the document sheet has been determined to be blank, in a manner that the number of pixels can be compared with the threshold value, and a changing unit that changes the threshold value.

Abstract translation: 图像读取器包括：读取单元，被配置为读取文档片上的图像以生成读取数据;计数单元，被配置为对具有多于预定灰度级的读取数据的像素数进行计数;确定单元 当由所述计数单元计数的像素数不超过阈值时，所述文档片材为空白;显示单元，被配置为显示由所述计数单元计数的像素数量和所述文档片材的阈值 已经被确定为空白，以像素的数量可以与阈值进行比较，以及改变单元改变阈值。

公开(公告)号：US20120043601A1

公开(公告)日：2012-02-23

申请号：US13275436

申请日：2011-10-18

Applicant: Takashi MAEDA ,  Yoshihisa Iwata

Inventor： Takashi MAEDA ,  Yoshihisa Iwata

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate.

Abstract translation: 在非易失性半导体存储器件中，通过在硅衬底上交替堆叠电介质膜和导电膜来形成层叠体，并且以矩阵形式形成沿堆叠方向延伸的多个通孔。 分路互连和位互连设置在堆叠体的上方。 导体支柱埋设在多个通孔中的分流互连的正下方配置的贯通孔的内侧，半导体柱埋设在剩余通孔的内部。 导电柱由金属或低电阻硅形成。 其上端部连接到分路互连，并且其下端部连接到形成在硅衬底的上层部分中的电池源。

公开(公告)号：US20110063916A1

公开(公告)日：2011-03-17

申请号：US12727827

申请日：2010-03-19

Applicant: Takashi MAEDA

Inventor： Takashi MAEDA

IPC: G11C16/02

CPC classification number: G11C16/04 ,  H01L27/11556 ,  H01L27/11578

Abstract: At least some of the memory transistors included in a first memory string are commonly connected to first conductive layers that are connected to at least some of the memory transistors included in a second memory string connected to the same third and fourth conductive layers as the first memory string. At least one of either the memory transistors or the back-gate transistor in the first memory string and at least one of either the memory transistors or the back-gate transistor in the second memory string are connected to the independent first or fifth conductive layers, respectively.

Abstract translation: 包括在第一存储器串中的至少一些存储晶体管共同连接到第一导电层，其连接到连接到与第一存储器相同的第三和第四导电层的第二存储器串中的至少一些存储晶体管 串。 第一存储器串中的存储晶体管或背栅晶体管中的至少一个以及第二存储器串中的存储晶体管或背栅晶体管中的至少一个连接到独立的第一或第五导电层， 分别。

公开(公告)号：US20120282493A1

公开(公告)日：2012-11-08

申请号：US13542907

申请日：2012-07-06

Applicant: Kouji KITSUNAI ,  Takashi MAEDA

Inventor： Kouji KITSUNAI ,  Takashi MAEDA

IPC: G11B5/73

CPC classification number: G11B5/7315 ,  G11B5/82

Abstract: A glass substrate for a magnetic disk, wherein, in regions with respect to two places arbitrarily selected on a surface of the glass substrate on its central portion side relative to its outer peripheral end, a surface shape with a shape wavelength in a band of 60 to 500 μm is extracted from surface shapes in each of the regions and, assuming that a root mean square roughness Rq of the surface shape is given as a microwaviness Rq, the difference between the microwavinesses Rq of the regions is 0.02 nm or less or the difference between standard deviations of the microwavinesses Rq of the regions is 0.04 nm or less.

Abstract translation: 一种磁盘用玻璃基板，其特征在于，在相对于其外周端部的中央部侧的玻璃基板的表面上任意选择的两个位置的区域中，形状波长为60nm的波长的表面形状 在每个区域中从表面形状提取至500μm，并且假设表面形状的均方根粗糙度Rq作为微波特性Rq，则区域的微波特性Rq之差为0.02nm以下，或者 区域的微波的标准偏差之间的差异为0.04nm以下。

公开(公告)号：US20120243314A1

公开(公告)日：2012-09-27

申请号：US13301948

申请日：2011-11-22

Applicant: Takashi MAEDA

Inventor： Takashi MAEDA

IPC: G11C16/04 ,  H01L29/792

CPC classification number: H01L27/11582 ,  H01L27/11565

Abstract: A nonvolatile semiconductor memory device according to one aspect includes a semiconductor substrate, a memory string, a plurality of first conductive layers, a second conductive layer, and a third conductive layer. The memory string has a plurality of memory cells, a dummy transistor and a back gate transistor connected in series in a direction perpendicular to the semiconductor substrate. The plurality of first conductive layers are electrically connected to gates of the memory cells. The second conductive layer is electrically connected to a gate of the dummy transistor. The third conductive layer is electrically connected to a gate of the back gate transistor. The second conductive layer is short-circuited with the third conductive layer.

Abstract translation: 根据一个方面的非易失性半导体存储器件包括半导体衬底，存储器串，多个第一导电层，第二导电层和第三导电层。 存储器串具有与垂直于半导体衬底的方向串联连接的多个存储单元，虚拟晶体管和背栅晶体管。 多个第一导电层电连接到存储单元的栅极。 第二导电层电连接到虚拟晶体管的栅极。 第三导电层电连接到背栅晶体管的栅极。 第二导电层与第三导电层短路。

公开(公告)号：US20120176836A1

公开(公告)日：2012-07-12

申请号：US13091589

申请日：2011-04-21

Applicant: Natsuki IGUCHI ,  Takashi MAEDA

Inventor： Natsuki IGUCHI ,  Takashi MAEDA

IPC: G11C16/28 ,  G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/10 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7926

Abstract: According to one embodiment, a non-volatile semiconductor memory device comprises memory strings. Each memory string comprises a semiconductor layer, control gates, a first selection gate, and a second selection gate. A semiconductor layer comprises a pair of pillar portions which extend in a vertical direction to a substrate, and a coupling portion formed to couple the pair of pillar portions. Control gates orthogonally intersect one of the pair of pillar portions or the other of the pair of pillar portions. A first selection gate orthogonally intersects one of the pair of pillar portions and is formed above the control gates. A second selection gate orthogonally intersects the other of the pair of pillar portions, is formed above the control gates, and is on the same level as the first selection gate as well as integrated with the first selection gate.

Abstract translation: 根据一个实施例，非易失性半导体存储器件包括存储器串。 每个存储器串包括半导体层，控制栅极，第一选择栅极和第二选择栅极。 半导体层包括在垂直方向上延伸到基板的一对柱部分和形成为耦合所述一对柱部分的联接部分。 控制栅极与一对柱部分中的一个或一对柱部分中的另一个正交相交。 第一选择栅极与一对柱部分中的一个正交相交并形成在控制栅极的上方。 与控制栅极之间形成与第一选择栅极相同的第二选择栅极，与第一选择栅极集成，与第一选择栅极成一体。

公开(公告)号：US20090242968A1

公开(公告)日：2009-10-01

申请号：US12408183

申请日：2009-03-20

Applicant: Takashi MAEDA ,  Yoshihisa Iwata

Inventor： Takashi MAEDA ,  Yoshihisa Iwata

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate.

Abstract translation: 在非易失性半导体存储器件中，通过在硅衬底上交替堆叠电介质膜和导电膜来形成层叠体，并且以矩阵形式形成沿堆叠方向延伸的多个通孔。 分路互连和位互连设置在堆叠体的上方。 导体支柱埋设在多个通孔中的分流互连的正下方配置的贯通孔的内侧，半导体柱埋设在剩余通孔的内部。 导电柱由金属或低电阻硅形成。 其上端部连接到分路互连，并且其下端部连接到形成在硅衬底的上层部分中的电池源。

公开(公告)号：US20140138898A1

公开(公告)日：2014-05-22

申请号：US14039490

申请日：2013-09-27

Applicant: Takashi MAEDA ,  Muneaki TAKAHATA ,  Yoshinori OSAKABE ,  Masayoshi OOSAKI

Inventor： Takashi MAEDA ,  Muneaki TAKAHATA ,  Yoshinori OSAKABE ,  Masayoshi OOSAKI

IPC: B65H7/20 ,  B65H3/06

CPC classification number: B65H7/20 ,  B65H3/06 ,  B65H3/063 ,  B65H5/062 ,  B65H5/26 ,  B65H7/02 ,  B65H2402/46 ,  B65H2404/1531 ,  B65H2405/3322 ,  B65H2511/11 ,  B65H2511/12 ,  B65H2511/415 ,  B65H2511/416 ,  B65H2513/10 ,  B65H2513/42 ,  B65H2801/39 ,  H04N1/00588 ,  H04N1/00652 ,  B65H2220/01 ,  B65H2220/03 ,  B65H2220/02

Abstract: In an image reading apparatus, it is judged whether an original sheet is either one of a first sheet type, whose sheet length is longer than or equal to a first conveyance distance and shorter than a second conveyance distance, and a second sheet type, whose sheet length is longer than or equal to the second conveyance path, the first conveyance distance being distance between a first conveyance roller and a second conveyance roller, the second conveyance distance being distance between a supply roller and the second conveyance roller. The original sheet is conveyed at a separation timing, when the original sheet separates away from the supply roller, at a speed that is smaller for a case where the original sheet is of the first sheet type than for a case where the original sheet is of the second sheet type. An image is read from the conveyed original sheet.

Abstract translation: 在图像读取装置中，判断原稿是否为纸张长度大于或等于第一输送距离并且短于第二输送距离的第一纸张类型和第二纸张类型中的任何一种， 片材长度大于或等于第二输送路径，第一输送距离是第一输送辊和第二输送辊之间的距离，第二输送距离是供给辊与第二输送辊之间的距离。 原稿在分离时被传送，当原稿片与供纸辊分离时，对于原纸为第一纸张类型的情况，原稿纸张的原始纸张的原始纸张数比原始纸张为 第二张纸张类型。 从传送的原稿中读取图像。

公开(公告)号：US20130258425A1

公开(公告)日：2013-10-03

申请号：US13795812

申请日：2013-03-12

Applicant: Takashi MAEDA ,  Yuki NAKAJIMA

Inventor： Takashi MAEDA ,  Yuki NAKAJIMA

IPC: H04N1/028

CPC classification number: H04N1/02815 ,  H04N1/00588 ,  H04N1/00657 ,  H04N1/12 ,  H04N1/193 ,  H04N1/2032 ,  H04N1/40056

Abstract: An image reading device includes a conveying unit, reading unit, and a control unit. The conveying unit conveys successive two sheets along a conveying path such that a gap is formed between the successive two sheets. The reading unit reads a sheet conveyed at a reading position in the conveying path. The reading unit has a light source and light-receiving unit. The control unit controls the light source to emit light at a first light intensity for a sheet that has reached the reading position. The light-receiving unit receives light reflected by the sheet present at the reading position. The control unit further controls the light source to emit a light at a second light intensity lower than the first light intensity during a period of time from when the reading unit has been read the preceding sheet to when the reading unit begins reading the subsequent sheet.

Abstract translation: 图像读取装置包括输送单元，读取单元和控制单元。 输送单元沿着输送路径输送连续的两张纸，使得在连续的两张纸之间形成间隙。 读取单元读取在输送路径中的读取位置传送的纸张。 读取单元具有光源和光接收单元。 控制单元控制光源以对于已经达到读取位置的片材的第一光强度发光。 光接收单元接收由存在于读取位置的纸张反射的光。 控制单元进一步控制光源在从读取单元已经读取前一张纸张到读取单元开始读取随后的纸张的时间段期间以比第一光强度低的第二光强度发光。