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    Switching circuit
    4.
    发明授权
    Switching circuit 有权
    开关电路

    公开(公告)号：US08766699B2

    公开(公告)日：2014-07-01

    申请号：US13490240

    申请日：2012-06-06

    申请人： Kazuhiro Fujikawa ,  Nobuo Shiga ,  Takashi Ohira ,  Kazuyuki Wada ,  Hiroshi Ishioka

    发明人： Kazuhiro Fujikawa ,  Nobuo Shiga ,  Takashi Ohira ,  Kazuyuki Wada ,  Kazuya Ishioka

    IPC分类号： H03K17/30

    CPC分类号： H03K17/04123 ,  H03K2217/0036 ,  H03K2217/0045 ,  Y10T307/747

    摘要： A switching circuit according to one embodiment includes first to fourth semiconductor switch elements. A pulse-like signal is applied to each input terminal of the switch elements such that when the first and fourth switch elements are in an ON (OFF) state, the remaining switch elements are in an OFF (ON) state. The switching circuit includes first and second capacitance elements. The first capacitance elements connected between an output terminal of the second semiconductor switch element and the second capacitance elements connected between an input terminal of the second semiconductor switch element and an output terminal of the fourth semiconductor switch element has a capacitance to reduce a parasitic capacitance between the input and output terminals of each of the fourth and second switch elements at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.

    摘要翻译： 根据一个实施例的开关电路包括第一至第四半导体开关元件。 脉冲状信号被施加到开关元件的每个输入端子，使得当第一和第四开关元件处于导通（OFF）状态时，剩余的开关元件处于断开（ON）状态。 开关电路包括第一和第二电容元件。 连接在第二半导体开关元件的输出端子和连接在第二半导体开关元件的输入端子和第四半导体开关元件的输出端子之间的第二电容元件之间的第一电容元件具有电容以减小第二半导体开关元件的输出端之间的寄生电容 以与脉冲状信号的时钟频率相同的频率N倍（N为1以上的整数）的第四开关元件和第二开关元件的输入输出端子。

    Switching circuit
    5.
    发明授权
    Switching circuit 有权
    开关电路

    公开(公告)号：US08760223B2

    公开(公告)日：2014-06-24

    申请号：US13490101

    申请日：2012-06-06

    申请人： Kazuhiro Fujikawa ,  Nobuo Shiga ,  Takashi Ohira ,  Kazuyuki Wada ,  Hiroshi Ishioka

    发明人： Kazuhiro Fujikawa ,  Nobuo Shiga ,  Takashi Ohira ,  Kazuyuki Wada ,  Kazuya Ishioka

    IPC分类号： H02M3/07

    CPC分类号： H03K17/04123 ,  H03K2217/0036 ,  H03K2217/0045 ,  H03K2217/009

    摘要： A switching circuit according to one embodiment is a switching circuit including at least one semiconductor switch element having an input, output, and a common terminals, a pulse-like signal being applied between the input and common terminals to switch a current between the output and common terminals. The switching circuit further includes a capacitance suppression element section connected at least one of between the input and output terminals, between the input terminal common terminals, and between the output and common terminals. The capacitance suppression element section reduces a parasitic capacitance between the terminals of the semiconductor switch element where the capacitance suppression element section is connected to less than that obtained when the capacitance suppression element section is not connected at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.

    摘要翻译： 根据一个实施例的开关电路是包括具有输入，输出和公共端子的至少一个半导体开关元件的开关电路，脉冲状信号被施加在输入端和公共端子之间以切换输出和 公共终端 开关电路还包括电容抑制元件部分，其连接在输入和输出端子之间，输入端子公共端子之间以及输出端子和公共端子之间的至少一个。 电容抑制元件部分减小了电容抑制元件部分连接的半导体开关元件的端子之间的寄生电容小于当电容抑制元件部分未以N倍的频率连接时获得的寄生电容（N为 1或更高）与脉冲状信号的时钟频率一样高。

    SWITCHING CIRCUIT
    6.
    发明申请
    SWITCHING CIRCUIT 有权
    切换电路

    公开(公告)号：US20120306288A1

    公开(公告)日：2012-12-06

    申请号：US13490240

    申请日：2012-06-06

    申请人： Kazuhiro Fujikawa ,  Nobuo Shiga ,  Takashi Ohira ,  Kazuyuki Wada ,  Kazuya Ishioka ,  Hiroshi Ishioka

    发明人： Kazuhiro Fujikawa ,  Nobuo Shiga ,  Takashi Ohira ,  Kazuyuki Wada ,  Kazuya Ishioka ,  Hiroshi Ishioka

    IPC分类号： H01H47/00

    CPC分类号： H03K17/04123 ,  H03K2217/0036 ,  H03K2217/0045 ,  Y10T307/747

    摘要： A switching circuit according to one embodiment includes first to fourth semiconductor switch elements. A pulse-like signal is applied to each input terminal of the switch elements such that when the first and fourth switch elements are in an ON (OFF) state, the remaining switch elements are in an OFF (ON) state. The switching circuit includes first and second capacitance elements. The first capacitance elements connected between an output terminal of the second semiconductor switch element and the second capacitance elements connected between an input terminal of the second semiconductor switch element and an output terminal of the fourth semiconductor switch element has a capacitance to reduce a parasitic capacitance between the input and output terminals of each of the fourth and second switch elements at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.

    摘要翻译： 根据一个实施例的开关电路包括第一至第四半导体开关元件。 脉冲状信号被施加到开关元件的每个输入端子，使得当第一和第四开关元件处于导通（OFF）状态时，剩余的开关元件处于断开（ON）状态。 开关电路包括第一和第二电容元件。 连接在第二半导体开关元件的输出端子和连接在第二半导体开关元件的输入端子和第四半导体开关元件的输出端子之间的第二电容元件之间的第一电容元件具有电容以减小第二半导体开关元件的输出端之间的寄生电容 以与脉冲状信号的时钟频率相同的频率N倍（N为1以上的整数）的第四开关元件和第二开关元件的输入输出端子。

    LATERAL JUNCTION FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
    7.
    发明申请
    LATERAL JUNCTION FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
    横向连接场效应晶体管及其制造方法

    公开(公告)号：US20090315082A1

    公开(公告)日：2009-12-24

    申请号：US12552212

    申请日：2009-09-01

    申请人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

    发明人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

    IPC分类号： H01L29/808

    CPC分类号： H01L29/0634 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/66893 ,  H01L29/808

    摘要： A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

    摘要翻译： 横向结型场效应晶体管包括布置在源极/漏极区之间的第三半导体层中的第一栅电极层，具有在第二半导体层上延伸的下表面，并且掺杂有比第二半导体层更重的p型杂质 以及布置在源极/漏极区域之间的第五半导体层中的第二栅极电极层，具有在第四半导体层上延伸的下表面，具有与第一栅极电极层基本相同的p型杂质浓度，以及 具有与第一栅极电极层相同的电位。 因此，横向结型场效应晶体管具有可以在保持良好的击穿电压特性的同时降低导通电阻的结构。

    Lateral Junction Field Effect Transistor and Method of Manufacturing The Same
    9.
    发明申请
    Lateral Junction Field Effect Transistor and Method of Manufacturing The Same 有权
    横向结场效应晶体管及其制造方法

    公开(公告)号：US20080277696A1

    公开(公告)日：2008-11-13

    申请号：US12179320

    申请日：2008-07-24

    申请人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

    发明人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

    IPC分类号： H01L29/808

    CPC分类号： H01L29/0634 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/66893 ,  H01L29/808

    摘要： A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

    摘要翻译： 横向结型场效应晶体管包括布置在源/漏区域之间的第三半导体层中的第一栅电极层，具有在第二半导体层上延伸的下表面，并且掺杂有比第二半导体层更重的p型杂质 以及布置在源极/漏极区域之间的第五半导体层中的第二栅极电极层，具有在第四半导体层上延伸的下表面，具有与第一栅极电极层基本相同的p型杂质浓度，以及 具有与第一栅极电极层相同的电位。 因此，横向结型场效应晶体管具有可以在保持良好的击穿电压特性的同时降低导通电阻的结构。

    Vertical junction field effect transistors, and methods of producing the vertical junction field effect transistors
    10.
    发明授权
    Vertical junction field effect transistors, and methods of producing the vertical junction field effect transistors 失效
    垂直结场效应晶体管，以及垂直结型场效应晶体管的制造方法

    公开(公告)号：US07750377B2

    公开(公告)日：2010-07-06

    申请号：US11770414

    申请日：2007-06-28

    申请人： Takashi Hoshino ,  Shin Harada ,  Kazuhiro Fujikawa ,  Satoshi Hatsukawa ,  Kenichi Hirotsu

    发明人： Takashi Hoshino ,  Shin Harada ,  Kazuhiro Fujikawa ,  Satoshi Hatsukawa ,  Kenichi Hirotsu

    IPC分类号： H01L29/80

    CPC分类号： H01L29/66068 ,  H01L29/0634 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/66909 ,  H01L29/8083

    摘要： A vertical JFET 1a according to the present invention has an n+ type drain semiconductor portion 2, an n-type drift semiconductor portion 3, a p+ type gate semiconductor portion 4, an n-type channel semiconductor portion 5, an n+ type source semiconductor portion 7, and a p+ type gate semiconductor portion 8. The n-type drift semiconductor portion 3 is placed on a principal surface of the n+ type drain semiconductor portion 2 and has first to fourth regions 3a to 3d extending in a direction intersecting with the principal surface. The p+ type gate semiconductor portion 4 is placed on the first to third regions 3a to 3c of the n-type drift semiconductor portion 3. The n-type channel semiconductor portion 5 is placed along the p+ type gate semiconductor portion 4 and is electrically connected to the fourth region 3d of the n-type drift semiconductor portion 3.

    摘要翻译： 根据本发明的垂直JFET 1a具有n +型漏极半导体部分2，n型漂移半导体部分3，p +型栅极半导体部分4，n型沟道半导体部分5，n +型源半导体部分 7和p +型栅极半导体部分8.n型漂移半导体部分3放置在n +型漏极半导体部分2的主表面上，并且具有在与主体相交的方向上延伸的第一至第四区域3a至3d 表面。 p +型栅极半导体部分4放置在n型漂移半导体部分3的第一至第三区域3a至3c上.n型沟道半导体部分5沿着p +型栅极半导体部分4放置并且电连接 到n型漂移半导体部分3的第四区域3d。