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公开(公告)号：US20110158354A1
公开(公告)日：2011-06-30
申请号：US12953832
申请日：2010-11-24
申请人： Takashi YOKOKAWA , Osamu Shinya , Hitoshi Sakai
发明人： Takashi YOKOKAWA , Osamu Shinya , Hitoshi Sakai
IPC分类号： H04L27/06
CPC分类号： H04L5/0007 , H04L1/0052 , H04L1/0071
摘要： Disclosed herein is a receiver including a receiving section, a first sorting section, a second sorting section, and a switching section.
摘要翻译： 本文公开了一种接收机，包括接收部分，第一分类部分，第二分类部分和切换部分。
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公开(公告)号：US08503583B2
公开(公告)日：2013-08-06
申请号：US12953832
申请日：2010-11-24
申请人： Takashi Yokokawa , Osamu Shinya , Hitoshi Sakai
发明人： Takashi Yokokawa , Osamu Shinya , Hitoshi Sakai
IPC分类号： H04L27/06
CPC分类号： H04L5/0007 , H04L1/0052 , H04L1/0071
摘要： A receiver that receives an Orthogonal Frequency Division Multiplexing (OFDM) signal obtained by modulating a common packet sequence and data packet sequence. The common packet sequence is made up of packets common to a plurality of streams. The data packet sequence is made up of packets specific to one of the plurality of streams. The receiver sorts the common packet sequence, obtained by demodulating the received OFDM signal, in the time domain, and sorts the data packet sequence, obtained by demodulating the received OFDM signal, in the time domain. The receiver then switches the output for error correction from the one sorting over to the other sorting if, while the one sorting supplies its output to the error correction, the other sorting completes its input of a predetermined unit of information to be processed.
摘要翻译： 接收器，其接收通过调制公共分组序列和数据分组序列而获得的正交频分复用（OFDM）信号。 公共分组序列由多个流公共的分组组成。 数据分组序列由特定于多个流之一的分组组成。 接收机对在时域中对接收到的OFDM信号进行解调而获得的公共分组序列进行排序，并对在时域中对接收到的OFDM信号进行解调而获得的数据分组序列进行分类。 然后，如果在一个排序将其输出提供给纠错的情况下，接收器将用于纠错的输出从一个排序切换到另一个分类，则另一排序完成其要处理的预定信息单元的输入。
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公开(公告)号：US08086934B2
公开(公告)日：2011-12-27
申请号：US11912481
申请日：2006-04-20
IPC分类号： H03M13/00
CPC分类号： H03M13/1168 , H03M13/1114 , H03M13/1137 , H03M13/116 , H03M13/6505 , H03M13/6566
摘要： A decoding apparatus and method are capable of decoding LDPC codes with a high degree of precision while preventing the circuit scale of the decoding apparatus from increasing. A computation section carries out a first computation process corresponding to three check-node processes by making use of decoding intermediate results supplied from a decoding intermediate result storage memory by way of a cyclic shift circuit, and stores the result of the first computation process in a decoding intermediate result storage memory. A computation section carries out a second computation process corresponding to six variable-node processes by making use of decoding intermediate results supplied from a decoding intermediate result storage memory by way of a cyclic shift circuit, and stores the decoding intermediate result in the decoding intermediate result storage memory.
摘要翻译： 解码装置和方法能够以高精度解码LDPC码，同时防止解码装置的电路规模增加。 计算部通过循环移位电路利用从解码中间结果存储存储器提供的解码中间结果，对与三个校验节点处理相对应的第一计算处理进行处理，并将第一计算处理的结果存储在 解码中间结果存储存储器。 计算部通过循环移位电路利用从解码中间结果存储存储器提供的解码中间结果，对与六个可变节点处理相对应的第二计算处理进行解码，并将解码中间结果存储在解码中间结果 存储内存
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公开(公告)号：US20090106622A1
公开(公告)日：2009-04-23
申请号：US12253347
申请日：2008-10-17
申请人： Takashi Yokokawa , Satoshi Okada , Osamu Shinya
发明人： Takashi Yokokawa , Satoshi Okada , Osamu Shinya
CPC分类号： H03M13/11 , H04L1/0052 , H04L1/0057 , H04L1/007
摘要： A receiving apparatus including, an LDPC decoder configured to decode both of the data signal and the transmission control signal, a data signal input buffer arranged before the LDPC decoder and configured to hold the received data signal and a transmission control signal input buffer arranged before the LDPC decoder and configured to hold the received transmission control signal, and a controller configured to select one of the data signal held in the data signal input buffer and the transmission control signal held in the transmission control signal input buffer as a signal subject to decoding and transmit the selected signal to the LDPC decoder to make the LDPC decoder decode the signal subject to decoding.
摘要翻译： 一种接收装置，包括：LDPC解码器，被配置为解码所述数据信号和所述传输控制信号;数据信号输入缓冲器，布置在所述LDPC解码器之前并被配置为保持所述接收的数据信号;以及传输控制信号输入缓冲器， LDPC解码器，被配置为保持所接收的发送控制信号，以及控制器，被配置为选择保持在数据信号输入缓冲器中的数据信号中的一个和保持在发送控制信号输入缓冲器中的发送控制信号作为经解码的信号;以及 将所选择的信号发送到LDPC解码器，以使LDPC解码器对经过解码的信号进行解码。
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公开(公告)号：US20120110415A1
公开(公告)日：2012-05-03
申请号：US13238397
申请日：2011-09-21
申请人： Takashi Yokokawa , Osamu Shinya , Yutaka Nakada , Ryoji Ikegaya
发明人： Takashi Yokokawa , Osamu Shinya , Yutaka Nakada , Ryoji Ikegaya
CPC分类号： H03M13/152 , H03M13/65 , H03M13/6502
摘要： The present disclosure provides a decoding apparatus including, a storage section configured to store a reception value, a detection section configured to detect an error in the reception value, an error correction section configured to correct an error detected by the detection section with respect to the reception value, and a control section configured to control reading of the reception value from the storage section, wherein the control section controls first reading such that the reception value is read into the detection section and, after detection of an error by the detection section, second reading such that substantially the same reception value as that in the first reading is read into the error correction section.
摘要翻译： 本公开提供了一种解码装置，包括：存储部，被配置为存储接收值;检测部，被配置为检测接收值中的误差;纠错部，被配置为校正由所述检测部检测到的相对于 接收值，以及控制部，其被配置为控制从所述存储部读取接收值，其中，所述控制部控制第一读取，使得所述接收值被读入所述检测部，并且在检测部检测到错误之后， 第二读取使得与第一读取中基本上相同的接收值被读入错误校正部分。
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公开(公告)号：US20090217121A1
公开(公告)日：2009-08-27
申请号：US11912481
申请日：2006-04-20
CPC分类号： H03M13/1168 , H03M13/1114 , H03M13/1137 , H03M13/116 , H03M13/6505 , H03M13/6566
摘要： The present invention relates to a decoding apparatus and a decoding method, which are capable of decoding LDPC codes with a high degree of precision while preventing the circuit scale of the decoding apparatus from increasing. A computation section 1102 carries out a first computation process corresponding to three check-node processes by making use of decoding intermediate results D1101 supplied from a decoding intermediate result storage memory 1104 by way of a cyclic shift circuit 1101, and stores the result of the first computation process in a decoding intermediate result storage memory 1103. A computation section 415 carries out a second computation process corresponding to six variable-node processes by making use of decoding intermediate results D414 supplied from a decoding intermediate result storage memory 1103 by way of a cyclic shift circuit, and stores the decoding intermediate result D415 in the decoding intermediate result storage memory 1104. The present invention can be applied to, for example, a tuner for receiving (digital) satellite broadcasts.
摘要翻译： 解码装置和解码方法技术领域本发明涉及一种能够在防止解码装置的电路规模增大的同时高精度地解码LDPC码的解码装置和解码方法。 计算部分1102通过利用通过循环移位电路1101从解码中间结果存储存储器1104提供的解码中间结果D1101来执行与三个校验节点处理相对应的第一计算处理，并且存储第一 在解码中间结果存储存储器1103中的计算处理。计算部415通过利用从解码中间结果存储存储器1103提供的解码中间结果D414通过循环的方式执行与六个可变节点处理相对应的第二计算处理 并将解码中间结果D415存储在解码中间结果存储存储器1104中。本发明可以应用于例如用于接收（数字）卫星广播的调谐器。
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公开(公告)号：US08176402B2
公开(公告)日：2012-05-08
申请号：US12110064
申请日：2008-04-25
IPC分类号： H03M13/00
CPC分类号： G06F11/1008 , G11B20/1833 , G11B20/1866
摘要： A decoding apparatus includes a memory and a receiving unit and is adapted to decode data in units of codewords each including a parity part. The memory has a storage capacity capable of storing at least data with a length equal to the length of one codeword. The receiving unit receives, as received values, elements of a codeword in a bit-interleaved form, performs bit deinterleaving and parity permutating on the received values, and stores the resultant received values in the memory.
摘要翻译： 解码装置包括存储器和接收单元，并且适于以包括奇偶校验部分的码字为单位对数据进行解码。 存储器具有能够存储长度等于一个码字的长度的至少数据的存储容量。 接收单元以比特交织形式接收码字的元素作为接收值，对接收到的值执行比特解交织和奇偶校验，并将所得到的接收值存储在存储器中。
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公开(公告)号：US07657820B2
公开(公告)日：2010-02-02
申请号：US11409237
申请日：2006-04-24
申请人： Takashi Yokokawa , Yuji Shinohara , Osamu Shinya
发明人： Takashi Yokokawa , Yuji Shinohara , Osamu Shinya
IPC分类号： H03M13/00
CPC分类号： H03M13/1111 , H03M13/1131 , H03M13/1134 , H03M13/1137 , H03M13/118 , H03M13/6577
摘要： A decoding device for decoding an LDPC (Low Density Parity Check) code. The decoding device may include a first operation unit for performing a check node operation for decoding the LDPC code, the operation including an operation of a nonlinear function and an operation of an inverse function of the nonlinear function; and a second operation unit for performing a variable node operation for decoding the LDPC code. The first operation unit includes a first converting unit for converting a first quantization value assigned to a numerical value into a second quantization value representing a numerical value with a higher precision than the first quantization value, and a second converting unit for converting the second quantization value into the first quantization value.
摘要翻译： 一种用于解码LDPC（低密度奇偶校验）码的解码装置。 解码装置可以包括用于执行用于对LDPC码进行解码的校验节点操作的第一操作单元，该操作包括非线性函数的操作和非线性函数的反函数的操作; 以及第二操作单元，用于执行用于对LDPC码进行解码的可变节点操作。 第一操作单元包括：第一转换单元，用于将分配给数值的第一量化值转换成表示具有比第一量化值更高的精度的数值的第二量化值;以及第二转换单元，用于将第二量化值 进入第一个量化值。
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公开(公告)号：US20080270876A1
公开(公告)日：2008-10-30
申请号：US12110064
申请日：2008-04-25
CPC分类号： G06F11/1008 , G11B20/1833 , G11B20/1866
摘要： A decoding apparatus includes a memory and a receiving unit and is adapted to decode data in units of codewords each including a parity part. The memory has a storage capacity capable of storing at least data with a length equal to the length of one codeword. The receiving unit receives, as received values, elements of a codeword in a bit-interleaved form, performs bit deinterleaving and parity permutating on the received values, and stores the resultant received values in the memory.
摘要翻译： 解码装置包括存储器和接收单元，并且适于以包括奇偶校验部分的码字为单位对数据进行解码。 存储器具有能够存储长度等于一个码字的长度的至少数据的存储容量。 接收单元以比特交织形式接收码字的元素作为接收值，对接收到的值执行比特解交织和奇偶校验，并将所得到的接收值存储在存储器中。
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公开(公告)号：US09172497B2
公开(公告)日：2015-10-27
申请号：US13885557
申请日：2011-11-14
CPC分类号： H04L1/004 , H03M13/1102 , H03M13/152 , H03M13/253 , H03M13/255 , H03M13/618 , H03M13/6362 , H03M13/6552 , H04L1/0043 , H04L1/0052 , H04L1/0057 , H04L1/0065 , H04L1/0068 , H04L1/0072
摘要： A data processing device and a data processing method that can readily process control data having its PAPR improved. In a transmission device, a padder pads control data necessary for demodulation with zeros as dummy data, and a scrambler scrambles the padded control data (post-padding control data). A replacement unit replaces scrambled dummy data in the scrambled post-padding control data with the dummy data, and a BCH encoder and an LDPC encoder perform BCH encoding and LDPC encoding as error correction encoding on the replacement data obtained through the replacement. A shortening unit performs shortening by deleting the dummy data contained in the LDPC code and puncturing the parity bits of the LDPC code. The device can be applied in cases where control data is subjected to error correction encoding and is then transmitted, for example.
摘要翻译： 能够容易地处理其PAPR的控制数据的数据处理装置和数据处理方法。 在传输装置中，焊盘将用于以零作为解调的解调所需的数据作为伪数据，并且扰频器对填充的控制数据进行加扰（后置填充控制数据）。 替换单元用伪数据替换加密的后置填充控制数据中的加密伪数据，并且BCH编码器和LDPC编码器对通过替换获得的替换数据执行BCH编码和LDPC编码作为纠错编码。 缩短单元通过删除包含在LDPC码中的伪数据并对该LDPC码的奇偶校验位进行穿孔来进行缩短。 例如，在控制数据经受纠错编码的情况下可以应用该装置。
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