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公开(公告)号：US08166363B2
公开(公告)日：2012-04-24
申请号：US12066641
申请日：2006-09-07
IPC分类号： H03M13/00
CPC分类号： H04L1/0052 , H03M13/1111 , H03M13/118 , H03M13/6577 , H04L1/0057
摘要： A decoding device and method for decoding an LDPC code with high accuracy while suppressing an increase of the scale of a device. A check node calculator (181) performs check node calculations including calculations of a nonlinear function φ(x) and its inverse function φ−1(x) of the nonlinear function so as to decode an LDPC code. A variable node calculator (103) performs variable node calculation of a variable node so as to decode the LDPC code. The check node calculator (181) has an LUT which receives a fixed-point quantized value expressing a numerical value with a fixed quantization width and outputs the result of the calculation of the nonlinear function φ(x) as a semi-floating point quantized value which is a bit sequence expressing a numerical value with a quantization width determined by a part of a bit sequence and an LUT which receives a semi-floating point quantized value and outputs the result of the calculation of the inverse function φ−1(x) as a fixed point quantized value. The invention can be applied to e.g., a tuner for receiving a satellite broadcast.
摘要翻译： 一种用于在抑制设备规模增加的同时高精度地解码LDPC码的解码装置和方法。 校验节点计算器（181）执行包括非线性函数的计算的校验节点计算（x）及其非线性函数的反函数＆phgr（-1），以解码LDPC码。 可变节点计算器（103）执行变量节点的可变节点计算，以解码LDPC码。 校验节点计算器（181）具有LUT，其接收表示具有固定量化宽度的数值的定点量化值，并将非线性函数＆amp;（x）的计算结果作为半浮点数量化 值，其是表示具有由位序列的一部分确定的量化宽度的数值的位序列和接收半浮点量化值的LUT，并输出反函数的计算结果＆phgr; -1（ x）作为固定点量化值。 本发明可以应用于例如用于接收卫星广播的调谐器。
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公开(公告)号：US20090304111A1
公开(公告)日：2009-12-10
申请号：US12066641
申请日：2006-09-07
IPC分类号： H03K9/00
CPC分类号： H04L1/0052 , H03M13/1111 , H03M13/118 , H03M13/6577 , H04L1/0057
摘要： A decoding device and method for decoding an LDPC code with high accuracy while suppressing an increase of the scale of a device. A check node calculator (181) performs check node calculations including calculations of a nonlinear function φ(x) and its inverse function φ−1(x) of the nonlinear function so as to decode an LDPC code. A variable node calculator (103) performs variable node calculation of a variable node so as to decode the LDPC code. The check node calculator (181) has an LUT which receives a fixed-point quantized value expressing a numerical value with a fixed quantization width and outputs the result of the calculation of the nonlinear function φ(x) as a semi-floating point quantized value which is a bit sequence expressing a numerical value with a quantization width determined by a part of a bit sequence and an LUT which receives a semi-floating point quantized value and outputs the result of the calculation of the inverse function φ−1(x) as a fixed point quantized value. The invention can be applied to e.g., a tuner for receiving a satellite broadcast.
摘要翻译： 一种用于在抑制设备规模增加的同时高精度地解码LDPC码的解码装置和方法。 校验节点计算器（181）执行包括非线性函数phi（x）及其反函数phi-1（x）的计算的校验节点计算，以解码LDPC码。 可变节点计算器（103）执行变量节点的可变节点计算，以解码LDPC码。 校验节点计算器（181）具有LUT，其接收具有固定量化宽度的表示数值的定点量化值，并将非线性函数phi（x）的计算结果输出为半浮点量化值 其是表示具有由位序列的一部分确定的量化宽度的数值的位序列和接收半浮点量化值的LUT，并输出反函数phi-1（x）的计算结果， 作为固定点量化值。 本发明可以应用于例如用于接收卫星广播的调谐器。
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公开(公告)号：US20060242536A1
公开(公告)日：2006-10-26
申请号：US11409237
申请日：2006-04-24
申请人： Takashi Yokokawa , Yuji Shinohara , Osamu Shinya
发明人： Takashi Yokokawa , Yuji Shinohara , Osamu Shinya
IPC分类号： H03M13/00
CPC分类号： H03M13/1111 , H03M13/1131 , H03M13/1134 , H03M13/1137 , H03M13/118 , H03M13/6577
摘要： The present invention provides a decoding device for decoding an LDPC (Low Density Parity Check) code. The decoding device include: a first operation unit for performing a check node operation for decoding the LDPC code, the operation including an operation of a nonlinear function and an operation of an inverse function of the nonlinear function; and a second operation unit for performing a variable node operation for decoding the LDPC code. The first operation unit includes a first converting unit for converting a first quantization value assigned to a numerical value into a second quantization value representing a numerical value with a higher precision than the first quantization value, and a second converting unit for converting the second quantization value into the first quantization value. In processing performed as the check node operation and the variable node operation, the first operation unit and the second operation unit use the second quantization value in processing from after the operation of the nonlinear function to the operation of the inverse function, and use the first quantization value in the other processing.
摘要翻译： 本发明提供一种用于解码LDPC（低密度奇偶校验）码的解码装置。 解码装置包括：第一操作单元，用于执行用于解码LDPC码的校验节点操作，该操作包括非线性函数的操作和非线性函数的反函数的操作; 以及第二操作单元，用于执行用于对LDPC码进行解码的可变节点操作。 第一操作单元包括：第一转换单元，用于将分配给数值的第一量化值转换成表示具有比第一量化值更高的精度的数值的第二量化值;以及第二转换单元，用于将第二量化值 进入第一个量化值。 在作为校验节点操作和可变节点操作执行的处理中，第一操作单元和第二操作单元使用从非线性函数操作之后的处理中的第二量化值到逆函数的操作，并且使用第一操作单元 其他处理中的量化值。
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公开(公告)号：US07657820B2
公开(公告)日：2010-02-02
申请号：US11409237
申请日：2006-04-24
申请人： Takashi Yokokawa , Yuji Shinohara , Osamu Shinya
发明人： Takashi Yokokawa , Yuji Shinohara , Osamu Shinya
IPC分类号： H03M13/00
CPC分类号： H03M13/1111 , H03M13/1131 , H03M13/1134 , H03M13/1137 , H03M13/118 , H03M13/6577
摘要： A decoding device for decoding an LDPC (Low Density Parity Check) code. The decoding device may include a first operation unit for performing a check node operation for decoding the LDPC code, the operation including an operation of a nonlinear function and an operation of an inverse function of the nonlinear function; and a second operation unit for performing a variable node operation for decoding the LDPC code. The first operation unit includes a first converting unit for converting a first quantization value assigned to a numerical value into a second quantization value representing a numerical value with a higher precision than the first quantization value, and a second converting unit for converting the second quantization value into the first quantization value.
摘要翻译： 一种用于解码LDPC（低密度奇偶校验）码的解码装置。 解码装置可以包括用于执行用于对LDPC码进行解码的校验节点操作的第一操作单元，该操作包括非线性函数的操作和非线性函数的反函数的操作; 以及第二操作单元，用于执行用于对LDPC码进行解码的可变节点操作。 第一操作单元包括：第一转换单元，用于将分配给数值的第一量化值转换成表示具有比第一量化值更高的精度的数值的第二量化值;以及第二转换单元，用于将第二量化值 进入第一个量化值。
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公开(公告)号：US20130311850A1
公开(公告)日：2013-11-21
申请号：US13982494
申请日：2012-02-01
IPC分类号： H03M13/09
CPC分类号： H03M13/09 , H03M13/036 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/271 , H03M13/2906 , H04L1/0045 , H04L1/0057 , H04L1/0065 , H04L1/0072 , H04L27/2626 , H04L27/2647
摘要： A data processing device and a data processing method capable of improving resistance to errors. Code bits of an LDPC code with a code length N of 16200 bits is written to, for example, eight storage units. When the code bits are stored in the storage units, a process of changing the storage start position of the code bits for each storage unit is performed as a sorting process of sorting the bits of the LDPC code such that a plurality of code bits corresponding to 1s in an arbitrary row of the parity check matrix of the LDPC code are not included in a single symbol which is read from the storage units. The present technology can be applied to, for example, the transmission of the LDPC code.
摘要翻译： 一种数据处理装置和能够改善抵抗误差的数据处理方法。 具有16200比特的码长N的LDPC码的码比特被写入例如八个存储单元。 当代码位被存储在存储单元中时，执行改变每个存储单元的代码位的存储开始位置的处理，作为对LDPC码的比特进行排序的排序处理，使得与 LDPC码的奇偶校验矩阵的任意行中的1个不包含在从存储单元读取的单个符号中。 本技术可以应用于例如LDPC码的传输。
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公开(公告)号：US20130254617A1
公开(公告)日：2013-09-26
申请号：US13818709
申请日：2011-08-25
IPC分类号： H03M13/05
CPC分类号： H03M13/05 , H03M13/036 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/271 , H03M13/2906 , H03M13/356 , H03M13/6552 , H04L27/36
摘要： The present invention relates to a data processing device and a data processing method capable of improving the resistance to error of data. An LDPC encoder 115 performs encoding using an LDPC code having a code length of 4320 bits and a coded rate of one of four types including ½, 7/12, ⅔, ¾. A parity check matrix H of the LDPC code is configured by arranging elements of 1's of an information matrix, which are determined based on a parity check matrix initial value table of the parity check matrix H representing positions of elements of 1's of the information matrix corresponding to an information length according to the code length and the coded rate for every 72 columns, in a column direction at a period of 72 columns. The parity check matrix initial value table, for example, is used for digital broadcasting for mobile terminals. The present invention can be applied in a case where LDPC encoding is performed.
摘要翻译： 本发明涉及能够提高数据的误差抵抗的数据处理装置和数据处理方法。 LDPC编码器115使用码长为4320位的LDPC码和包括½，7 / 12,2 / 3，¾的四种类型中的一种的编码速率进行编码。 通过布置基于奇偶校验矩阵H的奇偶校验矩阵初始值表确定的信息矩阵的1的元素来表示LDPC码的奇偶校验矩阵H，该奇偶校验矩阵初始值表示对应于信息矩阵的1的元素的位置 根据每72列的码长和编码速率在72列的列方向上的信息长度。 奇偶校验矩阵初始值表例如用于移动终端的数字广播。 本发明可以应用于执行LDPC编码的情况。
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7.发明授权Data processing device and data processing method for encoding/decoding information bits 有权用于对信息位进行编码/解码的数据处理装置和数据处理方法公开(公告)号：US09106256B2
公开(公告)日：2015-08-11
申请号：US13818709
申请日：2011-08-25
IPC分类号： H03M13/00 , H03M13/05 , H03M13/03 , H03M13/11 , H03M13/25 , H03M13/27 , H03M13/29 , H03M13/35 , H04L27/36 , H03M13/15
CPC分类号： H03M13/05 , H03M13/036 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/271 , H03M13/2906 , H03M13/356 , H03M13/6552 , H04L27/36
摘要： A data processing device and a data processing method capable of improving the resistance to error of data. An LDPC encoder performs encoding using an LDPC code having a code length of 4320 bits and a coded rate of one of four types including ½, 7/12, ⅔, ¾. A parity check matrix H of the LDPC code is configured by arranging elements of 1's of an information matrix, which are determined based on a parity check matrix initial value table of the parity check matrix H representing positions of elements of 1's of the information matrix corresponding to an information length according to the code length and the coded rate for every 72 columns, in a column direction at a period of 72 columns. The parity check matrix initial value table, for example, is used for digital broadcasting for mobile terminals.
摘要翻译： 一种数据处理装置和数据处理方法，能够提高数据的误差抵抗能力。 LDPC编码器使用码长为4320位的LDPC码和包括½，7/12，⅔，¾的四种类型之一的编码速率来执行编码。 通过布置基于奇偶校验矩阵H的奇偶校验矩阵初始值表确定的信息矩阵的1的元素来表示LDPC码的奇偶校验矩阵H，该奇偶校验矩阵初始值表示对应于信息矩阵的1的元素的位置 根据每72列的码长和编码速率在72列的列方向上的信息长度。 奇偶校验矩阵初始值表例如用于移动终端的数字广播。
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公开(公告)号：US09094043B2
公开(公告)日：2015-07-28
申请号：US13982494
申请日：2012-02-01
IPC分类号： H03M13/00 , H03M13/09 , H03M13/03 , H03M13/11 , H03M13/25 , H03M13/27 , H03M13/29 , H04L1/00 , H03M13/15 , H04L27/26
CPC分类号： H03M13/09 , H03M13/036 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/271 , H03M13/2906 , H04L1/0045 , H04L1/0057 , H04L1/0065 , H04L1/0072 , H04L27/2626 , H04L27/2647
摘要： A data processing device and a data processing method capable of improving resistance to errors. Code bits of an LDPC code with a code length N of 16200 bits is written to, for example, eight storage units. When the code bits are stored in the storage units, a process of changing the storage start position of the code bits for each storage unit is performed as a sorting process of sorting the bits of the LDPC code such that a plurality of code bits corresponding to 1s in an arbitrary row of the parity check matrix of the LDPC code are not included in a single symbol which is read from the storage units. The present technology can be applied to, for example, the transmission of the LDPC code.
摘要翻译： 一种数据处理装置和能够改善抵抗误差的数据处理方法。 具有16200比特的码长N的LDPC码的码比特被写入例如八个存储单元。 当代码位被存储在存储单元中时，执行改变每个存储单元的代码位的存储开始位置的处理，作为对LDPC码的比特进行排序的排序处理，使得与 LDPC码的奇偶校验矩阵的任意行中的1个不包含在从存储单元读取的单个符号中。 本技术可以应用于例如LDPC码的传输。
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公开(公告)号：US08887030B2
公开(公告)日：2014-11-11
申请号：US13579735
申请日：2011-02-18
申请人： Nabil Loghin , Lothar Stadelmeier , Joerg Robert , Samuel Asangbeng Atungsiri , Makiko Yamamoto , Yuji Shinohara , Lui Sakai , Takashi Yokokawa
发明人： Nabil Loghin , Lothar Stadelmeier , Joerg Robert , Samuel Asangbeng Atungsiri , Makiko Yamamoto , Yuji Shinohara , Lui Sakai , Takashi Yokokawa
CPC分类号： H03M13/11 , H03M13/1165 , H03M13/3761 , H03M13/6519 , H04L1/0036 , H04L1/0045 , H04L1/0057 , H04L1/0059 , H04L1/0068 , H04L1/0083 , H04L2001/0098
摘要： The present invention relates to an encoder for error correction code encoding input data words (D) into codewords (Z1, Z2), comprising: an encoder input (1451) for receiving input data words (D) each comprising a first number Kldpc of information symbols, an encoding means (1452) for encoding an input data word (D) into a codeword (Z1, Z2, Z3, Z4) such that a codeword comprises a basic codeword portion (B) including a data portion (D) and a basic parity portion (Pb) of a second number Nldpc−Kldpc of basic parity symbols, and an auxiliary codeword portion (A) including an auxiliary parity portion (Pa) of a third number MIR of auxiliary parity symbols, wherein said encoding means (14) is adapted i) for generating said basic codeword portion (B) from an input data word (D) according to a first code, wherein a basic parity symbol is generated by accumulating an information symbol at a parity symbol address determined according to a first address generation rule, and ii) for generating said auxiliary codeword portion (A) from an input data word (D) according to a second code, wherein an auxiliary parity symbol is generated by accumulating an information symbol m at a parity symbol address γ, wherein said parity symbol addresses γ are determined according to a second address generation rule Nldpc−Kldpc+{x+m mod Ga×QIR} mod MIR if x>Nldpc−Kldpc, wherein x denotes the addresses of a parity symbol accumulator corresponding to the first information symbol of a group of size Ga and QIR is an auxiliary code rate dependent, predefined constant, and an encoder output (1454) for outputting said codewords (Z1, Z2).
摘要翻译： 本发明涉及一种用于将输入数据字（D）编码成码字（Z1，Z2）的纠错码的编码器，包括：编码器输入端（1451），用于接收输入数据字（D），每个输入数据字包括第一数字信号Kldpc 符号，用于将输入数据字（D）编码为码字（Z1，Z2，Z3，Z4）的编码装置（1452），使得码字包括基本码字部分（B），其包括数据部分（D）和 基本奇偶校验符号的第二编号Nldpc-Kldpc的基本奇偶校验部分（Pb）和包括辅助奇偶校验符号的第三数量MIR的辅助奇偶校验部分（Pa）的辅助码字部分（A），其中所述编码装置 ）适于i）用于根据第一代码从输入数据字（D）产生所述基本码字部分（B），其中通过在根据第一代码确定的奇偶校验符号地址处累积信息符号来生成基本奇偶校验符号 地址生成规则，和ii）生成s 根据第二代码从输入数据字（D）辅助辅助码字部分（A），其中通过在奇偶校验符号地址γ处累积信息符号m来生成辅助奇偶校验符号，其中所述奇偶校验符号地址γ根据 如果x> Nldpc-Kldpc，则到第二地址生成规则Nldpc-Kldpc + {x + m mod Ga×QIR} mod MIR，其中x表示对应于大小为Ga的组的第一信息符号的奇偶校验符号累加器的地址， QIR是辅助代码速率相关的预定义常数，以及用于输出所述码字（Z1，Z2）的编码器输出（1454）。
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公开(公告)号：US08767881B2
公开(公告)日：2014-07-01
申请号：US13236706
申请日：2011-09-20
申请人： Takashi Yokokawa , Ryoji Ikegaya , Yuji Shinohara
发明人： Takashi Yokokawa , Ryoji Ikegaya , Yuji Shinohara
CPC分类号： H04L1/0047 , H04L1/0019 , H04L1/0057 , H04L1/0071 , H04L27/38 , H04L2001/0093
摘要： A signal processing apparatus is disclosed which includes: a detection section configured such that based on a result of the error correction of a signal generated by a single carrier system, the detection section detects the presence or absence of spectrum inversion in the signal; and a selection section configured such that if the detection section detects the spectrum inversion, the selection section selects the spectrally inverted signal as the signal subject to the error correction, and that if the detection section does not detect the spectrum inversion, then the selection selects the spectrally uninverted signal as the signal subject to the error correction.
摘要翻译： 公开了一种信号处理装置，包括：检测部，被配置为基于由单载波系统生成的信号的纠错结果，检测部检测信号中是否存在频谱反转; 以及选择部分，其被配置为使得如果检测部分检测到频谱反转，则选择部分选择频谱反转的信号作为经过纠错的信号，并且如果检测部分没有检测到频谱反转，则选择选择 作为经过纠错的信号的光谱未反相信号。
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