公开(公告)号：US5442226A

公开(公告)日：1995-08-15

申请号：US51780

申请日：1993-04-26

Applicant: Takeo Maeda ,  Hiroshi Gojohbori ,  Takeo Nakayama

Inventor： Takeo Maeda ,  Hiroshi Gojohbori ,  Takeo Nakayama

IPC: H01L21/8249 ,  H01L27/06 ,  H01L29/417 ,  H01L29/735 ,  H01L29/43

CPC classification number: H01L27/0623 ,  H01L29/41708

Abstract: In a semiconductor device, an emitter electrode has a polysilicon layer provided in a first contact hole and on a first insulating film. The polysilicon layer is in contact with an emitter region and is covered with a metal layer. A second contact hole is provided on a part of a second insulating film located on a substantially flat portion of the metal layer. A third contact hole is provided in those portions of the first insulating film and a second insulating layer which are located on a base region.

Abstract translation: 在半导体器件中，发射极电极具有设置在第一接触孔中的第一绝缘膜上的多晶硅层。 多晶硅层与发射极区域接触并被金属层覆盖。 第二接触孔设置在位于金属层的基本平坦部分上的第二绝缘膜的一部分上。 第三接触孔设置在位于基底区域的第一绝缘膜和第二绝缘层的那些部分中。

公开(公告)号：US5075752A

公开(公告)日：1991-12-24

申请号：US480762

申请日：1990-02-16

Applicant: Takeo Maeda ,  Syuso Fujii

Inventor： Takeo Maeda ,  Syuso Fujii

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/10 ,  H01L27/11 ,  H01L29/732

CPC classification number: H01L27/11 ,  H01L27/0623

Abstract: A Bi-CMOS semiconductor device includes a P-type semiconductor substrate, an N-type buried layer formed in the semiconductor substrate, a P-type well region formed on the buried layer, and an N-channel MOS transistor formed in a first predetermined area of the well region. The Bi-CMOS semiconductor device further includes an N-type surrounding layer formed to surround the well region in cooperation with the buried layer. The surrounding layer electrically isolates the well region from the substrate and the other P-type well region.

公开(公告)号：US3997825A

公开(公告)日：1976-12-14

申请号：US512924

申请日：1974-10-07

Applicant: Kunio Miyasita ,  Hironori Okuda ,  Yasuyuki Sugiura ,  Takeo Maeda ,  Yasuo Matsuda ,  Kazuo Honda

Inventor： Kunio Miyasita ,  Hironori Okuda ,  Yasuyuki Sugiura ,  Takeo Maeda ,  Yasuo Matsuda ,  Kazuo Honda

IPC: H02P27/06 ,  H02P5/74 ,  H02P6/08 ,  H02P6/22 ,  H02P25/02 ,  H02P5/34

CPC classification number: H02P5/74 ,  H02P25/03

Abstract: In the control of a synchronous motor driven by a power converter of voltage source type, the phase of the current flowing into the motor is detected and gate signals are produced on the basis of the phase of the current, so that the output frequency of the power converter is controlled by the gate signals so as to control the motor.

Abstract translation: 在由电压源式电力转换器驱动的同步电动机的控制中，检测流入电动机的电流的相位，并根据电流的相位产生门信号，使得输出频率 功率转换器由门信号控制，以控制电机。

公开(公告)号：US3939387A

公开(公告)日：1976-02-17

申请号：US462534

申请日：1974-04-19

Applicant: Takeo Maeda

Inventor： Takeo Maeda

IPC: H02M1/14 ,  H02M5/45 ,  H02M7/48 ,  H02P27/06 ,  H02P5/40

CPC classification number: H02P27/06 ,  H02M1/14 ,  H02M5/4505 ,  H02P2201/03

Abstract: In a variable frequency power converter of a current type for driving an AC motor including a rectifier, an inverter, and a smoothing reactor disposed on a DC transmission line between the rectifier and the inverter, there are provided a series circuit having a switching circuit and a smoothing capacitor on the DC input side of the inverter and a feedback circuit having controlled rectifier elements and commutation reactors for feeding back the reactive power of the AC motor. The power converter operates as a current type converter until the output frequency of the converter reaches a predetermined value under the condition that the switching circuit and the controlled rectifier elements are non-conductive, and operates as a voltage type converter when the output frequency has reached the predetermined value under the condition that the switching circuit and the controlled rectifier elements are conductive.

Abstract translation: 在用于驱动包括整流器，逆变器和设置在整流器与逆变器之间的直流传输线上的平滑电抗器的交流电动机的电流型变频电力变换器中，提供一种具有开关电路和 在逆变器的直流输入侧的平滑电容器和具有可控整流元件的反馈电路和用于反馈交流电动机的无功功率的换向电抗器。 电源转换器作为电流型转换器工作，直到转换器的输出频率在开关电路和可控整流元件不导通的条件下达到预定值，并且当输出频率达到时作为电压型转换器工作 在开关电路和可控整流元件导通的条件下的预定值。

公开(公告)号：US5512772A

公开(公告)日：1996-04-30

申请号：US309034

申请日：1994-09-20

Applicant: Takeo Maeda ,  Hiroshi Momose ,  Yukihiro Urakawa ,  Masataka Matsui

Inventor： Takeo Maeda ,  Hiroshi Momose ,  Yukihiro Urakawa ,  Masataka Matsui

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/165 ,  H01L29/737 ,  H01L27/02 ,  H01L29/161

CPC classification number: H01L27/0623 ,  H01L29/7378

Abstract: A semiconductor device of this invention includes a bipolar transistor and MOS transistors which are formed on the same semiconductor substrate. The bipolar transistor is hetero-bipolar transistor having a hetero junction. The hetero-bipolar transistor is a bipolar transistor of double-hetero structure in which a material used for forming the base region thereof has a band gap narrower than a material used for forming the emitter and collector regions thereof.

Abstract translation: 本发明的半导体器件包括形成在同一半导体衬底上的双极晶体管和MOS晶体管。 双极晶体管是具有异质结的异双极晶体管。 异双极晶体管是双异质结构的双极晶体管，其中用于形成其基极区的材料的带隙比用于形成其发射极和集电极区域的材料窄。

公开(公告)号：US5485034A

公开(公告)日：1996-01-16

申请号：US344694

申请日：1994-11-18

Applicant: Takeo Maeda ,  Hiroshi Gojohbori ,  Yoshitaka Tsunashima

Inventor： Takeo Maeda ,  Hiroshi Gojohbori ,  Yoshitaka Tsunashima

IPC: H01L29/73 ,  H01L21/331 ,  H01L27/06 ,  H01L29/10 ,  H01L29/732 ,  H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC classification number: H01L29/7322 ,  H01L27/0623 ,  H01L29/1004

Abstract: A semiconductor device of this invention includes an N-type semiconductor region functioning as a collector of a bipolar transistor, a silicon dioxide film doped with boron and formed in contact with the surface of the N-type semiconductor region, a P-type semiconductor region formed in contact with the silicon dioxide film doped with boron in the N-type semiconductor region and functioning as a base of the bipolar transistor, and an N-type semiconductor region formed in the P-type semiconductor region and functioning as an emitter of the bipolar transistor.

Abstract translation: 本发明的半导体器件包括用作双极晶体管的集电极的N型半导体区域，掺杂有硼并与N型半导体区域的表面接触形成的二氧化硅膜，P型半导体区域 形成为与N型半导体区域中掺杂有硼的二氧化硅膜接触并用作双极晶体管的基极，并且形成在P型半导体区域中并用作发光体的N型半导体区域 双极晶体管。

公开(公告)号：US5341021A

公开(公告)日：1994-08-23

申请号：US849102

申请日：1992-03-09

Applicant: Takeo Maeda ,  Hiroshi Momose

Inventor： Takeo Maeda ,  Hiroshi Momose

IPC: H01L27/10 ,  H01L21/331 ,  H01L27/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/73 ,  H01L29/732 ,  H01L29/40 ,  H01L27/082 ,  H01L29/70

CPC classification number: H01L27/0623 ,  H01L29/41708 ,  H01L29/42304

Abstract: A contact hole for guiding an emitter electrode of bipolar transistors continuously arrayed and a contact hole for guiding a base electrode are positioned not to be arranged in the continuous array direction of the bipolar transistors. Also, the emitter electrode and the base electrode are respectively drawn from these contact holes in two directions different from the continuous array direction of the bipolar transistors. At least one of the base electrode and the emitter electrode is formed on a conductive layer of a polycide structure contacting an active region in a substrate to be connected.

Abstract translation: 用于引导连续排列的双极晶体管的发射电极的接触孔和用于引导基极的接触孔不被布置在双极晶体管的连续阵列方向上。 此外，发射电极和基极电极分别从与双极晶体管的连续阵列方向不同的两个方向从这些接触孔拉出。 基极和发射电极中的至少一个形成在与要连接的基板中的有源区接触的多晶硅结构的导电层上。

公开(公告)号：US5340751A

公开(公告)日：1994-08-23

申请号：US793540

申请日：1991-11-18

Applicant: Takeo Maeda ,  Hiroshi Momose

Inventor： Takeo Maeda ,  Hiroshi Momose

IPC: H01L21/285 ,  H01L21/331 ,  H01L21/8249 ,  H01L2/265

CPC classification number: H01L29/66272 ,  H01L21/28525 ,  H01L21/8249 ,  Y10S148/009

Abstract: A method of manufacturing a semiconductor device. A semiconductor substrate is prepared and a gate oxide film is formed on a surface of the semiconductor substrate. The gate oxide film is selectively removed to expose portions of the semiconductor substrate and a first polysilicon layer is formed on a resultant semiconductor structure. Impurities are implanted in the polysilicon layer and a resultant semiconductor structure is annealed to activate the impurities. The first polysilicon layer is patterned to form a base electrode of the bipolar transistor and a gate and/or drain electrode of the MOS transistor. An insulating layer is then formed on a resultant semiconductor structure. Portions of the semiconductor substrate are then selectively exposed and a second polysilicon layer is formed on a resultant semiconductor structure. The second polysilicon layer is then patterned to form an emitter electrode of the bipolar transistor.

Abstract translation: 一种制造半导体器件的方法。 制备半导体衬底，并且在半导体衬底的表面上形成栅极氧化膜。 选择性地去除栅极氧化膜以暴露半导体衬底的部分，并且在所得半导体结构上形成第一多晶硅层。 将杂质注入多晶硅层，并将所得半导体结构退火以活化杂质。 图案化第一多晶硅层以形成双极晶体管的基极和MOS晶体管的栅极和/或漏电极。 然后在所得半导体结构上形成绝缘层。 然后选择性地暴露半导体衬底的部分，并且在所得半导体结构上形成第二多晶硅层。 然后将第二多晶硅层图案化以形成双极晶体管的发射极。

公开(公告)号：US5243557A

公开(公告)日：1993-09-07

申请号：US985109

申请日：1992-12-03

Applicant: Takeo Maeda ,  Yukari Unno ,  Hiroshi Momose ,  Masataka Matsui

Inventor： Takeo Maeda ,  Yukari Unno ,  Hiroshi Momose ,  Masataka Matsui

IPC: G11C11/413 ,  G11C8/08 ,  G11C11/415 ,  H01L27/10

CPC classification number: G11C8/08

Abstract: Disclosed here in is a semiconductor integrated circuit comprising a substrate, a memory cell array having a plurality of memory cells arranged in rows and columns, a plurality of word lines, and a plurality of bit lines, and a plurality of word-line drive circuits located near the memory cell array. Each of the word-line drive circuits is a Bi-NMOS circuit which comprises a bipolar transistor for pulling up the potential of the word line and an N-channel MOS transistor for pulling down the potential of the word line. The collector layers of the bipolar transistors are formed of one and the same layer.

Abstract translation: 这里公开的是一种半导体集成电路，包括基板，存储单元阵列，具有排列成行和列的多个存储单元，多个字线和多个位线，以及多个字线驱动电路 位于存储单元阵列附近。 每个字线驱动电路是一个Bi-NMOS电路，它包括用于提高字线电位的双极晶体管和用于下拉字线电位的N沟道MOS晶体管。 双极晶体管的集电极层由同一层形成。

公开(公告)号：US5091322A

公开(公告)日：1992-02-25

申请号：US572136

申请日：1990-08-22

Applicant: Takeo Maeda ,  Hiroshi Momose

Inventor： Takeo Maeda ,  Hiroshi Momose

IPC: H01L29/73 ,  H01L21/285 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732

CPC classification number: H01L29/66272 ,  H01L21/28525 ,  H01L21/8249 ,  Y10S148/009

Abstract: A method of manufacturing a semiconductor device. A semiconductor substrate is prepared and a gate oxide film is formed on a surface of the semiconductor substrate. The gate oxide film is selectively removed to expose portions of the semiconductor substrate and a first polysilicon layer is formed on a resultant semiconductor structure. Impurities are implanted in the polysilicon layer and a resultant semiconductor structure is annealed to activate the impurities. The first polysilicon layer is patterned to form a base electrode of the bipolar transistor and a gate and/or drain electrode of the MOS transistor. An insulating layer is then formed on a resultant semiconductor structure. Portions of the semiconductor substrate are then selectively exposed and a second polysilicon layer is formed on a resultant semiconductor structure. The second polysilicon layer is then patterned to form an emitter electrode of the bipolar transistor.

Abstract translation: 一种制造半导体器件的方法。 制备半导体衬底，并且在半导体衬底的表面上形成栅极氧化膜。 选择性地去除栅极氧化膜以暴露半导体衬底的部分，并且在所得半导体结构上形成第一多晶硅层。 将杂质注入多晶硅层，并将所得半导体结构退火以活化杂质。 图案化第一多晶硅层以形成双极晶体管的基极和MOS晶体管的栅极和/或漏电极。 然后在所得半导体结构上形成绝缘层。 然后选择性地暴露半导体衬底的部分，并且在所得半导体结构上形成第二多晶硅层。 然后将第二多晶硅层图案化以形成双极晶体管的发射极。