公开(公告)号：US5295107A

公开(公告)日：1994-03-15

申请号：US24074

申请日：1993-03-01

申请人： Takeshi Okazawa ,  Ken-Ichi Oyama ,  Hiroki Shirai

发明人： Takeshi Okazawa ,  Ken-Ichi Oyama ,  Hiroki Shirai

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  G11C7/00

CPC分类号： G11C16/3409 ,  G11C16/16

摘要： A method of controlling the nonvolatile memory device comprising making over-erasing simultaneously a set of EEPROM elements and then setting simultaneously the threshold voltages of said set of EEPROM elements back to the specified threshold-voltage values. The over-erasing is accomplished by applying a first pulse between the source and the control gate to induce the first FN current across the gate insulating film. The setting-back is accomplished by applying a second pulse between the well and the control gate to induce the second FN current flowing reversely to the first FN current.

摘要翻译： 一种控制非易失性存储器件的方法，包括同时进行一组EEPROM元件的过度擦除，然后同时将所述EEPROM元件组的阈值电压恢复到指定的阈值电压值。 通过在源极和控制栅极之间施加第一脉冲以引导跨越栅极绝缘膜的第一FN电流来实现过擦除。 通过在阱和控制栅之间施加第二脉冲以引起与第一FN电流相反流动的第二FN电流来实现回调。

公开(公告)号：US6017793A

公开(公告)日：2000-01-25

申请号：US887408

申请日：1997-07-02

申请人： Ken-Ichi Oyama

发明人： Ken-Ichi Oyama

IPC分类号： H01L21/8247 ,  H01L21/265 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7885 ,  H01L21/26586

摘要： A method is provided for forming a memory cell in a nonvolatile semiconductor memory device having MOSFET configuration from a data memory section having two-layer gate construction and series select transistors formed between a control gate connected to the data memory section and the exposed side walls of the semiconductor substrate. According to this method, a polycrystalline semiconductor film that forms floating gates and an underlying gate oxide film are processed by dry etching using a photoresist. Next, the semiconductor substrate is cut to a prescribed depth by dry etching to expose side walls of the semiconductor substrate, following which impurities are ion injected into the semiconductor substrate to form a diffused impurity layer. Finally, an intergate insulation film that forms a control gate and a polycrystalline semiconductor film are stacked and processed.

摘要翻译： 提供一种用于在具有MOSFET配置的非易失性半导体存储器件中形成存储单元的方法，所述非易失性半导体存储器件具有来自具有两层栅极结构的数据存储部分和形成在连接到数据存储器部分的控制栅极与暴露的侧面 半导体衬底。 根据该方法，通过使用光致抗蚀剂的干蚀刻来处理形成浮栅和下层栅氧化膜的多晶半导体膜。 接下来，通过干蚀刻将半导体衬底切割成规定的深度，以暴露半导体衬底的侧壁，随后将杂质离子注入到半导体衬底中以形成漫射杂质层。 最后，堆叠并处理形成控制栅极和多晶半导体膜的隔间绝缘膜。

公开(公告)号：US5637897A

公开(公告)日：1997-06-10

申请号：US606477

申请日：1996-03-04

申请人： Ken-Ichi Oyama

发明人： Ken-Ichi Oyama

IPC分类号： G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11534 ,  G11C16/0425 ,  G11C2216/04

摘要： A non-volatile semiconductor memory, called EPROM has a plurality of memory cells arrayed in a matrix and each having a laminate gate structure including a part of a strip control gate and a separate floating gate. A plurality of erasing gates is disposed in one of each two of spaces formed between two adjacent gate structures. Other of the each two of the spaces is filled with a laminate including a silicon nitride film and a silicon oxide film overlying the silicon nitride film. The erasing gates and the laminates are arranged alternately, so that the laminates do not cover the erasing gates. Difference in level between the memory cell section and the peripheral section is reduced to thereby prevent breakage of interconnects overlying the erasing gates. Etching of the substrate surface can be avoided to thereby obtain an improvement in the yield of the memory device.

摘要翻译： 称为EPROM的非易失性半导体存储器具有以矩阵形式排列的多个存储单元，每个存储单元具有包括带状控制栅极和单独浮置栅极的一部分的叠层栅极结构。 多个擦除栅极设置在形成在两个相邻栅极结构之间的每两个空间之一中。 在每个两个空间中的其它空间中填充有包括氮化硅膜和覆盖氮化硅膜的氧化硅膜的层压体。 擦除栅极和层叠体交替布置，使得层压体不覆盖擦除栅极。 减小了存储单元部分和周边部分之间的电平差，从而防止在擦除栅极上方的互连线断裂。 可以避免衬底表面的蚀刻，从而获得存储器件的产量的提高。

公开(公告)号：US5636168A

公开(公告)日：1997-06-03

申请号：US547322

申请日：1995-10-24

申请人： Ken-Ichi Oyama

发明人： Ken-Ichi Oyama

IPC分类号： G11C17/00 ,  G11C29/00 ,  G11C29/52 ,  G11C29/56 ,  G11C11/40

CPC分类号： G11C29/52

摘要： A method for testing nonvolatile memory device includes the steps of forming a block including a test row and a first and a second decoding row, by connecting the sources of the memory cells in the test row together to form a common source line, connecting each column of memory cells in the three rows in series, connecting the drains of the memory cells in the second decoding row together to form a common drain line, erasing the memory cells in the first and second decoding rows, successively programming and erasing the memory cells in the test row, and measuring a first drain current flowing through the common drain line with respect to the voltage of the word line of the test row. If the first drain current exhibits a negative threshold voltage, an over-erased memory cell exists in the test row. Thereafter, the total drain current of the memory cell other than the over-erased memory cell and the drain current of the over-erased memory cell can be separately measured for analyzing the tunnel oxide film of the memory cells.

摘要翻译： 一种用于测试非易失性存储器件的方法包括以下步骤：通过将测试行中的存储单元的源连接在一起以形成公共源极线，形成包括测试行和第一和第二解码行的块，连接每个列 串联的三行存储单元，将第二解码列中的存储单元的漏极连接在一起形成公共漏极线，擦除第一和第二解码行中的存储单元，连续编程和擦除存储单元的存储单元 测试行，并且相对于测试行的字线的电压测量流过公共漏极线的第一漏极电流。 如果第一漏极电流呈现负阈值电压，则在测试行中存在过擦除的存储器单元。 此后，可以单独测量除过擦除的存储单元之外的存储单元的总漏极电流和过擦除的存储单元的漏极电流，以分析存储单元的隧道氧化物膜。

公开(公告)号：US5880499A

公开(公告)日：1999-03-09

申请号：US919681

申请日：1997-08-28

申请人： Ken-Ichi Oyama

发明人： Ken-Ichi Oyama

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/06

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/66825 ,  H01L29/7885 ,  H01L21/26586

摘要： A non-volatile semiconductor memory device formed on a semiconductor substrate of a first conductivity type. The semiconductor memory including a plurality of recessed portions formed on a surface of the semiconductor substrate. The recessed portions having a sidewall and a bottom at which the semiconductor substrate is exposed. A gate oxide film is also directly formed on a surface of the semiconductor substrate other than the recessed portions. A floating gate electrode is formed on the gate oxide film. A source region and a drain region of a second conductivity type is formed in the semiconductor substrate at the bottom of the recessed portion and on opposing sides of the floating gate electrode. An intergate insulation film is formed on the semiconductor substrate to cover a top surface and sidewalls of the floating gate electrode, a sidewall of the recessed portion, the source region and drain region. A control gate electrode is further formed on the intergate insulation film. The intergate insulation film is in direct contact with the sidewall of the recessed portion so that the sidewall of the semiconductor substrate adjacent to the intergate insulation film forms a channel region of a field effect transistor.

摘要翻译： 形成在第一导电类型的半导体衬底上的非易失性半导体存储器件。 半导体存储器包括形成在半导体衬底的表面上的多个凹部。 凹部具有暴露半导体基板的侧壁和底部。 栅极氧化膜也直接形成在除了凹部之外的半导体衬底的表面上。 在栅极氧化膜上形成浮栅电极。 在半导体衬底中，在凹部的底部和浮置栅电极的相对侧上形成第二导电类型的源极区域和漏极区域。 栅极绝缘膜形成在半导体衬底上以覆盖浮动栅电极的顶表面和侧壁，凹陷部分的侧壁，源极区和漏极区。 在栅间绝缘膜上进一步形成控制栅电极。 隔间绝缘膜与凹部的侧壁直接接触，使得与栅极间绝缘膜相邻的半导体衬底的侧壁形成场效应晶体管的沟道区。

公开(公告)号：US5546339A

公开(公告)日：1996-08-13

申请号：US439458

申请日：1995-05-11

申请人： Ken-Ichi Oyama

发明人： Ken-Ichi Oyama

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C11/34

CPC分类号： G11C16/10 ,  G11C16/3427

摘要： When a write operation is indicated, a control circuit which receives the power supply voltage, generates a write control signal C, two power source voltages V1 and V2 for write which are 2 V and 10 V, respectively. Upon receipt of the write control signal C a row decoder 103 brings the word line corresponding to the memory cell transistor to be written in to 10 V and the other wordlines to 2 V. Upon receipt of the write control signal C a source line control circuit 105 brings the source line corresponding to the memory cell transistor to be written in to 0 V and the other source lines to 5 V.

摘要翻译： 当指示写入操作时，接收电源电压的控制电路产生分别为2V和10V的写入控制信号C，用于写入的两个电源电压V1和V2。 在写入控制信号C接收到时，行解码器103将对应于要写入的存储单元晶体管的字线输入10V，将另一个字线带到2V。在接收到写入控制信号C时，源极线控制电路 105将与要写入的存储单元晶体管对应的源极线导入0V，而将其它源极线导至5V。