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    Heterojunction bipolar transistor and method for fabricating the same
    1.
    发明授权
    Heterojunction bipolar transistor and method for fabricating the same 失效
    异质结双极晶体管及其制造方法

    公开(公告)号：US06821870B2

    公开(公告)日：2004-11-23

    申请号：US10224468

    申请日：2002-08-21

    申请人： Takeshi Takagi ,  Koichiro Yuki ,  Kenji Toyoda ,  Yoshihiko Kanzawa

    发明人： Takeshi Takagi ,  Koichiro Yuki ,  Kenji Toyoda ,  Yoshihiko Kanzawa

    IPC分类号： H01L2122

    CPC分类号： H01L29/7378 ,  H01L29/161 ,  H01L29/66242

    摘要： A heterojunction bipolar transistor is fabricated by stacking a Si collector layer, a SiGeC base layer and a Si emitter layer in this order. By making the amount of a lattice strain in the SiGeC base layer on the Si collector layer 1.0% or less, the band gap can be narrower than the band gap of the conventional practical SiGe (the Ge content is about 10%), and good crystalline can be maintained after a heat treatment. As a result, a narrow band gap base with no practical inconvenience can be realized.

    摘要翻译： 通过依次堆叠Si集电极层，SiGeC基极层和Si发射极层来制造异质结双极晶体管。 通过使Si集电体层的SiGeC基底层的晶格应变量为1.0％以下，带隙可以窄于现有实际SiGe的带隙（Ge含量为10％左右），良好 结晶可以在热处理后保持。 结果，可以实现没有实际麻烦的窄带隙基。

    Semiconductor device and method for fabricating the same
    4.
    发明授权
    Semiconductor device and method for fabricating the same 失效
    半导体装置及其制造方法

    公开(公告)号：US06399993B1

    公开(公告)日：2002-06-04

    申请号：US09786551

    申请日：2001-03-07

    申请人： Teruhito Ohnishi ,  Akira Asai ,  Takeshi Takagi ,  Tohru Saitoh ,  Yo Ichikawa ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Koji Katayama ,  Yoshihiko Kanzawa

    发明人： Teruhito Ohnishi ,  Akira Asai ,  Takeshi Takagi ,  Tohru Saitoh ,  Yo Ichikawa ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Koji Katayama ,  Yoshihiko Kanzawa

    IPC分类号： H01L2972

    CPC分类号： H01L21/76237 ,  H01L21/8249

    摘要： In a bipolar transistor block, a base layer (20a) of SiGe single crystals and an emitter layer (26) of almost 100% of Si single crystals are stacked in this order over a collector diffused layer (9). Over both edges of the base layer (20a), a base undercoat insulating film (5a) and base extended electrodes (22) made of polysilicon are provided. The base layer (20a) has a peripheral portion with a thickness equal to that of the base undercoat insulating film (5a) and a center portion thicker than the peripheral portion. The base undercoat insulating film (5a) and gate insulating films (5b and 5c) for a CMOS block are made of the same oxide film. A stress resulting from a difference in thermal expansion coefficient between the SiGe layer as the base layer and the base undercoat insulating film 5a can be reduced, and a highly reliable BiCMOS device is realized.

    摘要翻译： 在双极晶体管块中，SiGe单晶的基极层（20a）和几乎100％的Si单晶的发射极层（26）依次层叠在集电极扩散层（9）上。 在基底层（20a）的两个边缘上设置有由多晶硅制成的基底底涂层绝缘膜（5a）和基底延伸电极（22）。 基底层（20a）具有与基底底涂层绝缘膜（5a）的厚度相等的周边部分和比周边部分厚的中心部分。 用于CMOS块的基底涂层绝缘膜（5a）和栅极绝缘膜（5b和5c）由相同的氧化物膜制成。 由于作为基底层的SiGe层与基底底涂层绝缘膜5a之间的热膨胀系数的差异导致的应力可以降低，并且实现了高可靠性的BiCMOS器件。

    Semiconductor device and method for fabricating the same
    5.
    发明授权
    Semiconductor device and method for fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US06713790B2

    公开(公告)日：2004-03-30

    申请号：US10212799

    申请日：2002-08-07

    申请人： Akira Asai ,  Teruhito Oonishi ,  Takeshi Takagi ,  Tohru Saitoh ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Yo Ichikawa

    发明人： Akira Asai ,  Teruhito Oonishi ,  Takeshi Takagi ,  Tohru Saitoh ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Yo Ichikawa

    IPC分类号： H01L31072

    CPC分类号： H01L29/66242 ,  H01L21/763 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/7378

    摘要： In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.

    摘要翻译： 在本发明的半导体装置的制造方法中，在被器件分离夹持的半导体基板的区域中形成有第一导电型的集电极层。 通过沉积在半导体衬底上的第一绝缘层形成集电极开口，使得集电极开口的范围覆盖集电极层和器件隔离的一部分。 在位于集电体开口内部的半导体基板的一部分上形成作为外部基底的第二导电类型的半导体层，同时在半导体衬底中形成与外部基底相同的导电类型的防漏层。 因此，有源区域比集电极开口窄，减小晶体管面积，同时最小化结漏电。

    Semiconductor device and method for fabricating the same
    6.
    发明授权
    Semiconductor device and method for fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US06455364B1

    公开(公告)日：2002-09-24

    申请号：US09526686

    申请日：2000-03-15

    申请人： Akira Asai ,  Teruhito Oonishi ,  Takeshi Takagi ,  Tohru Saitoh ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Yo Ichikawa

    发明人： Akira Asai ,  Teruhito Oonishi ,  Takeshi Takagi ,  Tohru Saitoh ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Yo Ichikawa

    IPC分类号： H01L218249

    CPC分类号： H01L29/66242 ,  H01L21/763 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/7378

    摘要： In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.

    摘要翻译： 在本发明的半导体装置的制造方法中，在被器件分离夹持的半导体基板的区域中形成有第一导电型的集电极层。 通过沉积在半导体衬底上的第一绝缘层形成集电极开口，使得集电极开口的范围覆盖集电极层和器件隔离的一部分。 在位于集电体开口内部的半导体基板的一部分上形成作为外部基底的第二导电类型的半导体层，同时在半导体衬底中形成与外部基底相同的导电类型的防漏层。 因此，有源区域比集电极开口窄，减小晶体管面积，同时最小化结漏电。

    Heterojunction bipolar transistor having reduced driving voltage requirements
    7.
    发明授权
    Heterojunction bipolar transistor having reduced driving voltage requirements 有权
    具有降低的驱动电压要求的异质结双极晶体管

    公开(公告)号：US07135721B2

    公开(公告)日：2006-11-14

    申请号：US10872477

    申请日：2004-06-22

    申请人： Kenji Toyoda ,  Koichiro Yuki ,  Takeshi Takagi ,  Teruhito Ohnishi ,  Minoru Kubo

    发明人： Kenji Toyoda ,  Koichiro Yuki ,  Takeshi Takagi ,  Teruhito Ohnishi ,  Minoru Kubo

    IPC分类号： H01L29/739 ,  H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0336

    CPC分类号： H01L29/7378

    摘要： The bipolar transistor of the present invention includes a Si collector buried layer, a first base region made of a SiGeC layer having a high C content, a second base region made of a SiGeC layer having a low C content or a SiGe layer, and a Si cap layer 14 including an emitter region. The C content is less than 0.8% in at least the emitter-side boundary portion of the second base region. This suppresses formation of recombination centers due to a high C content in a depletion layer at the emitter-base junction, and improves electric characteristics such as the gain thanks to reduction in recombination current, while low-voltage driving is maintained.

    摘要翻译： 本发明的双极晶体管包括Si集电极掩埋层，由具有高C含量的SiGeC层制成的第一基极区域，具有低C含量的SiGeC层或SiGe层制成的第二基极区域，以及 Si覆盖层14包括发射极区域。 至少在第二基极区域的发射极边界部分中，C含量小于0.8％。 这抑制了由于在发射极 - 基极结处的耗尽层中的高C含量而导致的复合中心的形成，并且由于复合电流的降低而改善了诸如增益的电特性，同时维持了低电压驱动。

    Heterojunction bipolar transistor
    8.
    发明授权
    Heterojunction bipolar transistor 有权

    公开(公告)号：US06759697B2

    公开(公告)日：2004-07-06

    申请号：US10461364

    申请日：2003-06-16

    申请人： Kenji Toyoda ,  Koichiro Yuki ,  Takeshi Takagi ,  Teruhito Ohnishi ,  Minoru Kubo

    发明人： Kenji Toyoda ,  Koichiro Yuki ,  Takeshi Takagi ,  Teruhito Ohnishi ,  Minoru Kubo

    IPC分类号： H01L29737

    CPC分类号： H01L29/7378

    摘要： The bipolar transistor of the present invention includes a Si collector buried layer, a first base region made of a SiGeC layer having a high C content, a second base region made of a SiGeC layer having a low C content or a SiGe layer, and a Si cap layer 14 including an emitter region. The C content is less than 0.8% in at least the emitter-side boundary portion of the second base region. This suppresses formation of recombination centers due to a high C content in a depletion layer at the emitter-base junction, and improves electric characteristics such as the gain thanks to reduction in recombination current, while low-voltage driving is maintained.

    Nonvolatile memory device and method for programming nonvolatile memory element
    9.
    发明授权
    Nonvolatile memory device and method for programming nonvolatile memory element 有权
    非易失性存储器件和非易失性存储元件的编程方法

    公开(公告)号：US08619460B2

    公开(公告)日：2013-12-31

    申请号：US13509616

    申请日：2011-10-26

    申请人： Yoshihiko Kanzawa ,  Takeshi Takagi

    发明人： Yoshihiko Kanzawa ,  Takeshi Takagi

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0007 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0076 ,  G11C2213/56 ,  G11C2213/76

    摘要： A nonvolatile memory device (800) includes a variable resistance nonvolatile memory element (100) and a control circuit (810). The control circuit (810) determines whether a resistance value of the nonvolatile memory element (100) in a high resistance state is equal to or greater than a predetermined threshold value. Moreover, if the resistance value of the nonvolatile memory element (100) in the high resistance state is smaller than the threshold value, the control circuit (810) applies a first voltage (VL1) to the nonvolatile memory element (100) to change a resistance state of the nonvolatile memory element (100) from the high resistance state to the low resistance state. Moreover, if the resistance value of the nonvolatile memory element (100) in the high resistance state is equal to or greater than the threshold value, the control circuit (810) applies to the nonvolatile memory element (100) a second voltage (VL2) an absolute value of which is smaller an absolute value of the first voltage (VL1) to change the resistance state of the nonvolatile memory element (100) from the high resistance state to the low resistance state.

    摘要翻译： 非易失性存储器件（800）包括可变电阻非易失性存储元件（100）和控制电路（810）。 控制电路（810）确定高电阻状态下的非易失性存储元件（100）的电阻值是否等于或大于预定阈值。 此外，如果高电阻状态下的非易失性存储元件（100）的电阻值小于阈值，则控制电路（810）向非易失性存储元件（100）施加第一电压（VL1） 非易失性存储元件（100）从高电阻状态到低电阻状态的电阻状态。 此外，如果高电阻状态下的非易失性存储元件（100）的电阻值为阈值以上，则控制电路（810）向非易失性存储元件（100）施加第二电压（VL2） 其绝对值对于将非易失性存储元件（100）的电阻状态从高电阻状态改变为低电阻状态的第一电压（VL1）的绝对值较小。