公开(公告)号：US07336123B2

公开(公告)日：2008-02-26

申请号：US11390116

申请日：2006-03-28

申请人： Takeshi Yoshida ,  Atsushi Iwata ,  Mamoru Sasaki ,  Takayuki Mashimo ,  Yoshihiro Masui ,  Junji Nakatsuka

发明人： Takeshi Yoshida ,  Atsushi Iwata ,  Mamoru Sasaki ,  Takayuki Mashimo ,  Yoshihiro Masui ,  Junji Nakatsuka

IPC分类号： H03F1/02

CPC分类号： H03F3/45775 ,  H03F3/393

摘要： In a chopper amplifier circuit operable at a low voltage utilizing a switched operational amplifier, a chopper modulator chopper-modulates an input signal according to a predetermined control signal, and outputs a chopper-modulated signal. An amplifier circuit constituted by the switched operational amplifier amplifies the chopper-modulated signal outputted from the chopper modulator, and outputs an amplified chopper-modulated signal. A chopper-demodulator of the switched operational amplifier chopper-demodulates the amplified chopper-modulated signal outputted from the amplifier circuit according to the control signal, and outputs a demodulated output signal as a chopper-amplified output signal from an output terminal. A chopper modulator chopper-modulates a demodulated signal outputted from the chopper demodulator according to the control signal, and outputs a chopper-modulated signal to an input terminal of the amplifier circuit.

摘要翻译： 在利用开关式运算放大器在低电压工作的斩波放大器电路中，斩波调制器根据预定的控制信号对输入信号进行斩波调制，并输出斩波调制信号。 由开关运算放大器构成的放大电路放大从斩波调制器输出的斩波调制信号，并输出放大的斩波调制信号。 切换运算放大器的斩波解调器根据控制信号对从放大器电路输出的放大的斩波调制信号进行斩波，并从输出端子输出作为斩波放大输出信号的解调输出信号。 斩波调制器根据控制信号对从斩波解调器输出的解调信号进行斩波调制，并将斩波调制信号输出到放大电路的输入端。

公开(公告)号：US20060244521A1

公开(公告)日：2006-11-02

申请号：US11390116

申请日：2006-03-28

申请人： Takeshi Yoshida ,  Atsushi Iwata ,  Mamoru Sasaki ,  Takayuki Mashimo ,  Yoshihiro Masui ,  Junji Nakatsuka

发明人： Takeshi Yoshida ,  Atsushi Iwata ,  Mamoru Sasaki ,  Takayuki Mashimo ,  Yoshihiro Masui ,  Junji Nakatsuka

IPC分类号： H03F1/02

CPC分类号： H03F3/45775 ,  H03F3/393

摘要： In a chopper amplifier circuit operable at a low voltage utilizing a switched operational amplifier, a chopper modulator chopper-modulates an input signal according to a predetermined control signal, and outputs a chopper-modulated signal. An amplifier circuit constituted by the switched operational amplifier amplifies the chopper-modulated signal outputted from the chopper modulator, and outputs an amplified chopper-modulated signal. A chopper-demodulator of the switched operational amplifier chopper-demodulates the amplified chopper-modulated signal outputted from the amplifier circuit according to the control signal, and outputs a demodulated output signal as a chopper-amplified output signal from an output terminal. A chopper modulator chopper-modulates a demodulated signal outputted from the chopper demodulator according to the control signal, and outputs a chopper-modulated signal to an input terminal of the amplifier circuit.

摘要翻译： 在利用开关式运算放大器在低电压工作的斩波放大器电路中，斩波调制器根据预定的控制信号对输入信号进行斩波调制，并输出斩波调制信号。 由开关运算放大器构成的放大电路放大从斩波调制器输出的斩波调制信号，并输出放大的斩波调制信号。 切换运算放大器的斩波解调器根据控制信号对从放大器电路输出的放大的斩波调制信号进行斩波，并从输出端子输出作为斩波放大输出信号的解调输出信号。 斩波调制器根据控制信号对从斩波解调器输出的解调信号进行斩波调制，并将斩波调制信号输出到放大电路的输入端。

公开(公告)号：US07301399B2

公开(公告)日：2007-11-27

申请号：US11287469

申请日：2005-11-28

申请人： Takeshi Yoshida ,  Atsushi Iwata ,  Mamoru Sasaki ,  Kunihiko Gotoh

发明人： Takeshi Yoshida ,  Atsushi Iwata ,  Mamoru Sasaki ,  Kunihiko Gotoh

IPC分类号： H03F3/18

CPC分类号： H03F3/45183 ,  H03F3/3022 ,  H03F3/347 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2203/30015 ,  H03F2203/45366

摘要： In a class AB CMOS output circuit provided with a CMOS circuit including first P and N channel transistors and operating by a predetermined operating current Io, a replica circuit is formed on a semiconductor substrate of the CMOS circuit, and includes a second P channel transistor having a size equal or similar to that of the first P channel transistor, and a second N channel transistor having a size equal or similar to that of the first N channel transistor. A bias voltage supply allows the second P and N channel transistors to operate based on a reference current Iref corresponding to the operating current Io, applies a first bias voltage as applied to the second P channel transistor to the first P channel transistor, and applies a second bias voltage as applied to the second N channel transistor to the first N channel transistor.

摘要翻译： 在具有CMOS电路的AB类CMOS输出电路中，包括第一P和N沟道晶体管并通过预定的工作电流I O 2进行操作，复制电路形成在CMOS电路的半导体衬底上， 并且包括具有与第一P沟道晶体管相同或相似的尺寸的第二P沟道晶体管，以及具有与第一N沟道晶体管的尺寸相等或相似的尺寸的第二N沟道晶体管。 偏置电压电源允许第二P沟道晶体管和N沟道晶体管基于对应于工作电流I 的参考电流Iref工作，将施加到第二P沟道晶体管的第一偏置电压施加到 第一P沟道晶体管，并将施加到第二N沟道晶体管的第二偏置电压施加到第一N沟道晶体管。

公开(公告)号：US20060114061A1

公开(公告)日：2006-06-01

申请号：US11287469

申请日：2005-11-28

申请人： Takeshi Yoshida ,  Atsushi Iwata ,  Mamoru Sasaki ,  Kunihiko Gotoh

发明人： Takeshi Yoshida ,  Atsushi Iwata ,  Mamoru Sasaki ,  Kunihiko Gotoh

IPC分类号： H03F3/18

CPC分类号： H03F3/45183 ,  H03F3/3022 ,  H03F3/347 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2203/30015 ,  H03F2203/45366

摘要： In a class AB CMOS output circuit provided with a CMOS circuit including first P and N channel transistors and operating by a predetermined operating current Io, a replica circuit is formed on a semiconductor substrate of the CMOS circuit, and includes a second P channel transistor having a size equal or similar to that of the first P channel transistor, and a second N channel transistor having a size equal or similar to that of the first N channel transistor. A bias voltage supply allows the second P and N channel transistors to operate based on a reference current Iref corresponding to the operating current Io, applies a first bias voltage as applied to the second P channel transistor to the first P channel transistor, and applies a second bias voltage as applied to the second N channel transistor to the first N channel transistor.

摘要翻译： 在具有CMOS电路的AB类CMOS输出电路中，包括第一P和N沟道晶体管并通过预定的工作电流I O 2进行操作，复制电路形成在CMOS电路的半导体衬底上， 并且包括具有与第一P沟道晶体管相同或相似的尺寸的第二P沟道晶体管，以及具有与第一N沟道晶体管的尺寸相等或相似的尺寸的第二N沟道晶体管。 偏置电压电源允许第二P沟道晶体管和N沟道晶体管基于对应于工作电流I 的参考电流Iref工作，将施加到第二P沟道晶体管的第一偏置电压施加到 第一P沟道晶体管，并将施加到第二N沟道晶体管的第二偏置电压施加到第一N沟道晶体管。

公开(公告)号：US20050200510A1

公开(公告)日：2005-09-15

申请号：US11029492

申请日：2005-01-06

申请人： Takeshi Yoshida ,  Atsushi Iwata ,  Mamoru Sasaki ,  Miho Akagi ,  Kunihiko Goto

发明人： Takeshi Yoshida ,  Atsushi Iwata ,  Mamoru Sasaki ,  Miho Akagi ,  Kunihiko Goto

IPC分类号： H03M1/38 ,  H03M1/12 ,  H03M1/46 ,  H03M1/80

CPC分类号： H03M1/1245 ,  H03M1/466 ,  H03M1/804

摘要： In a sampling and holding, a control logic circuit connects another end of each capacitor of a DA converter to a ground potential, and outputs a sampled input analog signal from a switched amplifier to one end of a hold capacitor to hold. In a successive approximation, it controls a switched amplifier to set an output terminal thereof to a high-impedance state and the hold capacitor to connect the one end thereof to the ground potential. Then, it switches over connection of another end of each capacitor from the ground potential to a power supply voltage based on a digital value held by a successive approximation register to output an output voltage from another end of the hold capacitor to a comparator, and compares the output voltage from another end thereof with an intermediate reference voltage to obtain a digital value from the successive approximation register.

摘要翻译： 在采样和保持中，控制逻辑电路将DA转换器的每个电容器的另一端连接到地电位，并且将来自开关放大器的采样输入模拟信号输出到保持电容器的一端以保持。 在逐次逼近中，它控制开关放大器将其输出端子设置为高阻抗状态，并且保持电容器将其一端连接到地电位。 然后，基于由逐次逼近寄存器保持的数字值将每个电容器的另一端从地电位切换到电源电压，以将输出电压从保持电容器的另一端输出到比较器，并将其进行比较 来自其另一端的输出电压具有中间参考电压，以从逐次逼近寄存器获得数字值。

公开(公告)号：US07015841B2

公开(公告)日：2006-03-21

申请号：US11029492

申请日：2005-01-06

申请人： Takeshi Yoshida ,  Atsushi Iwata ,  Mamoru Sasaki ,  Miho Akagi ,  Kunihiko Goto

发明人： Takeshi Yoshida ,  Atsushi Iwata ,  Mamoru Sasaki ,  Miho Akagi ,  Kunihiko Goto

IPC分类号： H03M1/10

CPC分类号： H03M1/1245 ,  H03M1/466 ,  H03M1/804

摘要： In a sampling and holding, a control logic circuit connects another end of each capacitor of a DA converter to a ground potential, and outputs a sampled input analog signal from a switched amplifier to one end of a hold capacitor to hold. In a successive approximation, it controls a switched amplifier to set an output terminal thereof to a high-impedance state and the hold capacitor to connect the one end thereof to the ground potential. Then, it switches over connection of another end of each capacitor from the ground potential to a power supply voltage based on a digital value held by a successive approximation register to output an output voltage from another end of the hold capacitor to a comparator, and compares the output voltage from another end thereof with an intermediate reference voltage to obtain a digital value from the successive approximation register.

摘要翻译： 在采样和保持中，控制逻辑电路将DA转换器的每个电容器的另一端连接到地电位，并且将来自开关放大器的采样输入模拟信号输出到保持电容器的一端以保持。 在逐次逼近中，它控制开关放大器将其输出端子设置为高阻抗状态，并且保持电容器将其一端连接到地电位。 然后，基于由逐次逼近寄存器保持的数字值将每个电容器的另一端从地电位切换到电源电压，以将输出电压从保持电容器的另一端输出到比较器，并将其进行比较 来自其另一端的输出电压具有中间参考电压，以从逐次逼近寄存器获得数字值。

公开(公告)号：US20070285179A1

公开(公告)日：2007-12-13

申请号：US11744694

申请日：2007-05-04

申请人： Hiroaki Ikeda ,  Mamoru Sasaki ,  Atsushi Iwata ,  Mitsuru Shiozaki ,  Atsushi Mori

发明人： Hiroaki Ikeda ,  Mamoru Sasaki ,  Atsushi Iwata ,  Mitsuru Shiozaki ,  Atsushi Mori

IPC分类号： H03B9/14

CPC分类号： H03B5/1841 ,  G06F1/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a grid-type high-speed clock signal distribution network capable of reducing a difference in amplitude of a standing wave on a transmission line and of supplying a signal from any position. The network for transmitting the clock signal is such that ends of the differential signal transmission line are connected via an inductor, a low-amplitude segment is eliminated by a phase shift in the inductor and a standing wave of substantially uniform phase and amplitude is produced, wherein the number of lines connected to the grid point is made the same for entire grid points.

摘要翻译： 提供了一种能够减小传输线上的驻波的幅度差并从任何位置提供信号的网格式的高速时钟信号分配网络。 用于发送时钟信号的网络使得差分信号传输线的端部经由电感器连接，通过电感器中的相移来消除低幅度段，并且产生基本均匀的相位和幅度的驻波， 其中连接到网格点的线数对于整个网格点是相同的。

公开(公告)号：US07545663B2

公开(公告)日：2009-06-09

申请号：US11440398

申请日：2006-05-25

申请人： Hiroaki Ikeda ,  Mamoru Sasaki ,  Atsushi Iwata

发明人： Hiroaki Ikeda ,  Mamoru Sasaki ,  Atsushi Iwata

IPC分类号： G11C5/06

CPC分类号： G11C7/1051 ,  G11C5/02 ,  G11C7/1039 ,  G11C7/1078 ,  G11C7/1087 ,  G11C2207/107 ,  H01L23/481 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/05599

摘要： Data transfer speed is increased in a semiconductor storage device in which the core unit and the interface unit are separate chips. The device has a plurality of core chips through in which a memory cell is formed, and an interface chip in which a peripheral circuit is formed for the memory cell. The plurality of core chips through have latch circuit units through for temporarily storing data to be outputted by the memory cell, and latch circuit units through for temporarily storing data to be inputted to the memory cell, respectively, and these latch circuit units through and latch circuit units through are connected in a cascade to the interface chip. Since the plurality of latch circuit units connected in a cascade can thereby perform a pipeline operation, it becomes possible to achieve high-speed data transfer.

摘要翻译： 在核心单元和接口单元是分离的芯片的半导体存储设备中，数据传输速度增加。 该装置具有通过其中形成有存储单元的多个核芯片，以及形成用于存储单元的外围电路的接口芯片。 多个核芯片通过具有用于临时存储由存储单元输出的数据的锁存电路单元，以及用于临时存储要输入到存储单元的数据的锁存电路单元，并且这些锁存电路单元通过和锁存 电路单元通过级联连接到接口芯片。 由于串联连接的多个锁存电路单元能够进行流水线运行，因此能够实现高速数据传送。

公开(公告)号：US20070005876A1

公开(公告)日：2007-01-04

申请号：US11440398

申请日：2006-05-25

申请人： Hiroaki Ikeda ,  Mamoru Sasaki ,  Atsushi Iwata

发明人： Hiroaki Ikeda ,  Mamoru Sasaki ,  Atsushi Iwata

IPC分类号： G06F12/00

CPC分类号： G11C7/1051 ,  G11C5/02 ,  G11C7/1039 ,  G11C7/1078 ,  G11C7/1087 ,  G11C2207/107 ,  H01L23/481 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/05599

摘要： Data transfer speed is increased in a semiconductor storage device in which the core unit and the interface unit are separate chips. The device has a plurality of core chips through in which a memory cell is formed, and an interface chip in which a peripheral circuit is formed for the memory cell. The plurality of core chips through have latch circuit units through for temporarily storing data to be outputted by the memory cell, and latch circuit units through for temporarily storing data to be inputted to the memory cell, respectively, and these latch circuit units through and latch circuit units through are connected in a cascade to the interface chip. Since the plurality of latch circuit units connected in a cascade can thereby perform a pipeline operation, it becomes possible to achieve high-speed data transfer.

摘要翻译： 在核心单元和接口单元是分离的芯片的半导体存储设备中，数据传输速度增加。 该装置具有通过其中形成有存储单元的多个核芯片，以及形成用于存储单元的外围电路的接口芯片。 多个核芯片通过具有用于临时存储由存储单元输出的数据的锁存电路单元，以及用于临时存储要输入到存储单元的数据的锁存电路单元，并且这些锁存电路单元通过和锁存 电路单元通过级联连接到接口芯片。 由于串联连接的多个锁存电路单元能够进行流水线运行，因此能够实现高速数据传送。

公开(公告)号：US07538603B2

公开(公告)日：2009-05-26

申请号：US11744694

申请日：2007-05-04

申请人： Hiroaki Ikeda ,  Mamoru Sasaki ,  Atsushi Iwata ,  Mitsuru Shiozaki ,  Atsushi Mori

发明人： Hiroaki Ikeda ,  Mamoru Sasaki ,  Atsushi Iwata ,  Mitsuru Shiozaki ,  Atsushi Mori

IPC分类号： H01L25/00

CPC分类号： H03B5/1841 ,  G06F1/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a grid-type high-speed clock signal distribution network capable of reducing a difference in amplitude of a standing wave on a transmission line and of supplying a signal from any position. The network for transmitting the clock signal is such that ends of the differential signal transmission line are connected via an inductor, a low-amplitude segment is eliminated by a phase shift in the inductor and a standing wave of substantially uniform phase and amplitude is produced, wherein the number of lines connected to the grid point is made the same for entire grid points.

摘要翻译： 提供了一种能够减小传输线上的驻波的幅度差并从任何位置提供信号的网格式的高速时钟信号分配网络。 用于发送时钟信号的网络使得差分信号传输线的端部经由电感器连接，通过电感器中的相移来消除低幅度段，并且产生基本均匀的相位和幅度的驻波， 其中连接到网格点的线数对于整个网格点是相同的。