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    Porous carbonaceous material, manufacturing method therefor and use thereof
    2.
    发明授权
    Porous carbonaceous material, manufacturing method therefor and use thereof 失效
    多孔碳质材料及其制造方法及其用途

    公开(公告)号：US06475461B1

    公开(公告)日：2002-11-05

    申请号：US08737806

    申请日：1996-11-27

    申请人： Takushi Ohsaki ,  Akira Wakaizumi ,  Takashi Inui ,  Akihiro Nakamura ,  Katsuyoshi Yanagita ,  Masayoshi Hayashida

    发明人： Takushi Ohsaki ,  Akira Wakaizumi ,  Takashi Inui ,  Akihiro Nakamura ,  Katsuyoshi Yanagita ,  Masayoshi Hayashida

    IPC分类号： C01B3110

    CPC分类号： H01G9/155 ,  B01J20/20 ,  B01J20/30 ,  B01J21/18 ,  B01J35/10 ,  C01B32/336 ,  C04B38/0022 ,  H01G11/34 ,  H01M4/96 ,  Y02C10/08 ,  Y02E60/13

    摘要： A halogen treatment is conducted comprising: a halogenation step wherein a halogenation heat treatment for preparing a halogenated carbonized charcoal is conducted in which the carbonized charcoal is brought into contact with halogen; and a dehalogenation step wherein a dehalogenation treatment is conducted in which a part of or all halogen atoms in the halogenated carbonized charcoal are eliminated. A porous carbonaceous material is obtained at a high yield, and the amounts of nitrogen, oxygen, carbon dioxide, and methane adsorbed by this porous carbonaceous material are large. When this porous carbonaceous material is used as an electrical double layer capacitor carbon, the electrostatic capacity is increased compared to conventional carbonaceous materials. Consequently, a carbonaceous material is obtained which has micopores and/or sub-micropores which are suitable for the adsorption of small molecules such as nitrogen, and for storage of electrochemical energy.

    摘要翻译： 进行卤素处理，包括：卤化步骤，其中进行用于制备卤化碳化炭的卤化热处理，其中碳化炭与卤素接触; 和脱卤步骤，其中进行脱卤处理，其中卤代碳化炭中的一部分或全部卤素原子被除去。 以高产率获得多孔碳质材料，并且由该多孔碳质材料吸附的氮，氧，二氧化碳和甲烷的量大。 当这种多孔碳质材料用作电双层电容器碳时，与常规碳质材料相比，静电容量增加。 因此，得到具有适于吸附小分子如氮气的微孔和/或亚微孔以及用于储存电化学能的碳质材料。

    Manufacturing method for carbon material for electrical double layer capacitor
    4.
    发明授权
    Manufacturing method for carbon material for electrical double layer capacitor 失效
    双电层电容器碳材料的制造方法

    公开(公告)号：US6013208A

    公开(公告)日：2000-01-11

    申请号：US75225

    申请日：1998-05-11

    申请人： Akihiro Nakamura ,  Tadayoshi Iwasaki ,  Takashi Inui ,  Toshiya Miyagawa ,  Yasuo Tatsumi

    发明人： Akihiro Nakamura ,  Tadayoshi Iwasaki ,  Takashi Inui ,  Toshiya Miyagawa ,  Yasuo Tatsumi

    IPC分类号： C01B32/336 ,  H01G9/00 ,  H01G11/22 ,  H01G11/24 ,  H01G11/38 ,  H01G11/44 ,  H01G11/58 ,  H01G11/86 ,  H01G9/155

    CPC分类号： H01G9/155 ,  Y02E60/13

    摘要： A carbonaceous material for an electrical double layer capacitor is produced by performing a halogenation treatment step wherein a halogenated dry-distilled charcoal is obtained by bringing a dry-distilled charcoal into contact with a halogen gas; a molding treatment step of adding a binding agent to the halogenated dry-distilled charcoal to form a molded article; and a dehalogenation treatment step wherein a part or all of the halogen in the molded article is eliminated. The carbonaceous material for an electrical double layer capacitor obtained by this method is impregnated with sulfuric acid to form a carbon electrode for an electrical double layer capacitor. This electrode is used to form an electrical double layer capacitor.

    摘要翻译： 通过进行卤化处理工序来制造双电层电容器用碳质材料，其中通过使干馏炭与卤素气体接触而获得卤化干馏炭; 将结合剂添加到卤化干馏炭以形成模制品的成型处理步骤; 和脱卤处理步骤，其中除去模制品中的部分或全部卤素。 通过该方法得到的双电层电容器用碳质材料用硫酸浸渍，形成双电层电容器的碳电极。 该电极用于形成双电层电容器。

    Displaying objects using group and object priority levels
    5.
    发明授权
    Displaying objects using group and object priority levels 有权
    使用组和对象优先级显示对象

    公开(公告)号：US07770132B2

    公开(公告)日：2010-08-03

    申请号：US12045839

    申请日：2008-03-11

    申请人： Takashi Inui ,  Mizuho Tadokoro

    发明人： Takashi Inui ,  Mizuho Tadokoro

    IPC分类号： G06F3/048

    CPC分类号： G09G5/14 ,  G06F9/451

    摘要： A display device which displays a plurality of objects on a screen has a group configuration storage section for storing association information indicating the association between each of the plurality of objects and one of a plurality of groups, a group priority level storage section for storing group display priority levels which are priority levels for displaying each of the objects associated with one of the groups at the front of the objects associated with the other groups, an object priority level storage section for storing object display priority levels which are priority levels for displaying one of the objects associated with one of the groups at the front of the others, an object priority level changing section for changing the object display priority level while the association information is maintained, and a display section for displaying the plurality of objects according to the group display priority levels and the object display priority levels.

    摘要翻译： 在屏幕上显示多个对象的显示装置具有：组配置存储部，用于存储指示多个对象中的每一个与多个组中的一个的关联的关联信息;组优先级存储部，用于存储组显示 优先级，其是用于显示与与其他组相关联的对象的前面的组中的一个组相关联的每个对象的优先级;对象优先级级别存储部分，用于存储作为用于显示其他组中的一个的优先级的对象显示优先级 与其他前面的组中的一个相关联的对象，用于在保持关联信息的同时改变对象显示优先级的对象优先级改变部分和根据组显示显示多个对象的显示部分 优先级和对象显示优先级。

    Adaptive battery control
    6.
    发明申请
    Adaptive battery control 有权
    自适应电池控制

    公开(公告)号：US20050156571A1

    公开(公告)日：2005-07-21

    申请号：US11020993

    申请日：2004-12-22

    申请人： Takashi Inui ,  Mizuho Tadokoro

    发明人： Takashi Inui ,  Mizuho Tadokoro

    IPC分类号： G06F1/28 ,  H02J7/00 ,  H02J7/34

    CPC分类号： H02J7/0075

    摘要： An information processing apparatus driven by an AC power supply or a rechargeable battery has a charge directing unit which initiates charging of the battery from the AC power supply, provided that the remaining amount of power of the battery is lower than a predetermined charge-start-criteria level and that the information processing apparatus is driven by the AC power supply. Also included is a drive history storage which stores a drive history including information indicating which of the AC power supply and the battery was driving the information processing apparatus in each time period in the past. A recharge-start-criteria-level-setting unit sets the charge-start-criteria level on the basis of the drive history.

    摘要翻译： 由AC电源或可再充电电池驱动的信息处理装置具有充电指示单元，该充电指示单元从AC电源开始对电池充电，只要电池的剩余电量低于预定充电开始时间， 信号处理装置由AC电源驱动。 还包括一个驱动历史存储器，其存储包括在过去的每个时间段中包括交流电源和电池正在驱动信息处理装置的信息的驱动历史。 充值启动标准级别设置单元根据驱动历史设置充电开始标准级别。

    Semiconductor memory device
    8.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5574693A

    公开(公告)日：1996-11-12

    申请号：US473405

    申请日：1995-06-07

    申请人： Takashi Inui ,  Kiyotaka Okuzawa ,  Yoshihiro Ogata

    发明人： Takashi Inui ,  Kiyotaka Okuzawa ,  Yoshihiro Ogata

    IPC分类号： B60R9/042 ,  G11C13/00

    CPC分类号： G11C8/08 ,  G11C11/401 ,  G11C2029/2602 ,  G11C29/34

    摘要： A semiconductor memory device characterized by the fact that the disturb test time of the semiconductor memory device can be shortened, and the power consumption can be cut.In the disturb test for the semiconductor memory device in this invention, multiple word lines are selected at the same time with a prescribed interval corresponding to the element isolation layout. As the word lines are selected corresponding to the element isolating layout, the interference caused by the element isolation state can be excluded. Since multiple word lines are selected at the same time, the time of operation can be shortened. Since the word lines are maintained in the selected state while the sense amplifiers are not reset, there is no increase in the power consumption although multiple word lines are selected at the same time.

    摘要翻译： 一种半导体存储器件，其特征在于可以缩短半导体存储器件的干扰测试时间，并且可以削减功耗。 在本发明的半导体存储器件的干扰测试中，以对应于元件隔离布局的规定间隔同时选择多个字线。 当对应于元件隔离布局选择字线时，可以排除由元件隔离状态引起的干扰。 由于同时选择多个字线，所以可以缩短操作时间。 由于在读出放大器未复位的同时，字线保持在选择状态，所以尽管同时选择了多个字线，功耗也没有增加。

    Semiconductor memory device
    9.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5455796A

    公开(公告)日：1995-10-03

    申请号：US105203

    申请日：1993-08-10

    申请人： Takashi Inui ,  Kiyotaka Okuzawa ,  Yoshihiro Ogata

    发明人： Takashi Inui ,  Kiyotaka Okuzawa ,  Yoshihiro Ogata

    IPC分类号： G11C11/401 ,  G11C11/407 ,  G11C29/12 ,  G11C29/34 ,  H01L27/10 ,  G11C11/40

    CPC分类号： G11C29/34

    摘要： A semiconductor memory device characterized by the fact that the disturb test time of the semiconductor memory/device can be shortened, and the power consumption can be cut.In the disturb test for the semiconductor memory device in this invention, multiple word lines are selected at the same time with a prescribed interval corresponding to the element isolation layout. As the word lines are selected corresponding to the element isolating layout, the interference caused by the element isolation state can be excluded. Since multiple word lines are selected at the same time, the time of operation can be shortened. Since the word lines are maintained in the selected state while the sense amplifiers are not reset, there is no increase in the power consumption although multiple word lines are selected at the same time.

    摘要翻译： 一种半导体存储器件，其特征在于可以缩短半导体存储器/器件的干扰测试时间，并且可以削减功耗。 在本发明的半导体存储器件的干扰测试中，以对应于元件隔离布局的规定间隔同时选择多个字线。 当对应于元件隔离布局选择字线时，可以排除由元件隔离状态引起的干扰。 由于同时选择多个字线，所以可以缩短操作时间。 由于在读出放大器未复位的同时，字线保持在选择状态，所以尽管同时选择了多个字线，功耗也没有增加。

    Data selector circuit and method of selecting format of data output from plural registers
    10.
    发明授权
    Data selector circuit and method of selecting format of data output from plural registers 失效
    数据选择电路及从多个寄存器输出数据格式的方法

    公开(公告)号：US5055717A

    公开(公告)日：1991-10-08

    申请号：US398339

    申请日：1989-08-24

    申请人： Atsushi Naito ,  Kiyoshi Nakatsuka ,  Seiichi Yamamoto ,  Takashi Inui ,  Tomohiro Suzuki

    发明人： Atsushi Naito ,  Kiyoshi Nakatsuka ,  Seiichi Yamamoto ,  Takashi Inui ,  Tomohiro Suzuki

    IPC分类号： G09G5/395 ,  G11C7/10

    CPC分类号： G11C7/1075 ,  G09G5/395 ,  G11C7/103

    摘要： Data selector circuit including a plurality of data registers connected in parallel via corresponding output buffers to a plurality of output drivers, wherein a decoder and selector portion is interposed between the output buffers and the output drivers for selectively providing one of a plurality of serial data output sequences from the data registers to the output drivers rather than a parallel data output format from the plurality of data registers which would otherwise occur. The decoder and selector portion is controlled by a partial address buffer which is provided with serial sequence selection data. Upon decoding the serial sequence selection data of the partial address buffer, a plurality of MOS transistors included in the selector portion are rendered conductive in sequence in response to respective control signals applied to the gates thereof to connect the plurality of data registers via their output buffers to respective output drivers in a sequence determined by the decoded selection data of the partial address buffer for serial data output in the selected serial data output sequence.

    摘要翻译： 数据选择器电路包括通过相应的输出缓冲器并行连接到多个输出驱动器的多个数据寄存器，其中解码器和选择器部分插在输出缓冲器和输出驱动器之间，用于选择性地提供多个串行数据输出 从数据寄存器到输出驱动器的序列，而不是否则将发生的多个数据寄存器的并行数据输出格式。 解码器和选择器部分由具有串行序列选择数据的部分地址缓冲器控制。 在对部分地址缓冲器的串行序列选择数据进行解码时，响应于施加到其栅极的相应控制信号，包括在选择器部分中的多个MOS晶体管依次被导通，以经由其输出缓冲器连接多个数据寄存器 以由所选择的串行数据输出序列中输出的串行数据的部分地址缓冲器的解码选择数据确定的序列分配给相应的输出驱动器。