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    Manufacturing method of semiconductor device
    1.
    发明授权
    Manufacturing method of semiconductor device 失效
    半导体器件的制造方法

    公开(公告)号：US07700448B2

    公开(公告)日：2010-04-20

    申请号：US12014136

    申请日：2008-01-15

    申请人： Takuya Futase ,  Keiichiro Kashihara ,  Shigenari Okada

    发明人： Takuya Futase ,  Keiichiro Kashihara ,  Shigenari Okada

    IPC分类号： H01L21/00

    CPC分类号： H01L29/7846 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/7843

    摘要： The performance of the semiconductor device which formed the metal silicide layer in the salicide process is improved. An element isolation region is formed in a semiconductor substrate by the STI method, a gate insulating film is formed, a gate electrode is formed, n+ type semiconductor region and p+ type semiconductor region for source/drains are formed, a metallic film is formed on a semiconductor substrate, and a barrier film is formed on a metallic film. And after forming the metal silicide layer to which a metallic film, and a gate electrode, n+ type semiconductor region and p+ type semiconductor region are made to react by performing first heat treatment, a barrier film, and an unreacted metallic film are removed, and the metal silicide layer is left. An element isolation region makes compressive stress act on a semiconductor substrate. A barrier film is a film which makes a semiconductor substrate generate tensile stress, and the metal silicide layer which consists of mono-silicide MSi of metallic element M which forms a metallic film is formed in the first heat treatment.

    摘要翻译： 提高了在自对准硅化物工艺中形成金属硅化物层的半导体器件的性能。 通过STI法在半导体衬底中形成元件隔离区域，形成栅极绝缘膜，形成栅电极，形成n +型半导体区域和形成用于源极/漏极的p +型半导体区域，金属膜形成在 半导体衬底和阻挡膜形成在金属膜上。 在形成通过进行第一热处理使金属膜和栅电极n +型半导体区域和p +型半导体区域形成反应的金属硅化物层之后，除去阻挡膜和未反应的金属膜， 留下金属硅化物层。 元件隔离区使压缩应力作用在半导体衬底上。 阻挡膜是使半导体基板产生拉伸应力的膜，在第一热处理中形成由形成金属膜的金属元素M的单硅化物MSi构成的金属硅化物层。

    MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    2.
    发明申请
    MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 失效
    半导体器件的制造方法

    公开(公告)号：US20080242035A1

    公开(公告)日：2008-10-02

    申请号：US12014136

    申请日：2008-01-15

    申请人： Takuya FUTASE ,  Keiichiro Kashihara ,  Shigenari Okada

    发明人： Takuya FUTASE ,  Keiichiro Kashihara ,  Shigenari Okada

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7846 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/7843

    摘要： The performance of the semiconductor device which formed the metal silicide layer in the salicide process is improved. An element isolation region is formed in a semiconductor substrate by the STI method, a gate insulating film is formed, a gate electrode is formed, n+ type semiconductor region and p+ type semiconductor region for source/drains are formed, a metallic film is formed on a semiconductor substrate, and a barrier film is formed on a metallic film. And after forming the metal silicide layer to which a metallic film, and a gate electrode, n+ type semiconductor region and p+ type semiconductor region are made to react by performing first heat treatment, a barrier film, and an unreacted metallic film are removed, and the metal silicide layer is left. An element isolation region makes compressive stress act on a semiconductor substrate. A barrier film is a film which makes a semiconductor substrate generate tensile stress, and the metal silicide layer which consists of mono-silicide MSi of metallic element M which forms a metallic film is formed in the first heat treatment.

    摘要翻译： 提高了在自对准硅化物工艺中形成金属硅化物层的半导体器件的性能。 通过STI法在半导体衬底中形成元件隔离区域，形成栅极绝缘膜，形成栅电极，n + +型半导体区域和p + 形成用于源极/漏极的半导体区域，在半导体衬底上形成金属膜，并且在金属膜上形成阻挡膜。 并且在形成金属硅化物层之后，通过执行第一次金属硅化物层使金属膜和栅极，n + +型半导体区域和p + +型半导体区域反应 除去热处理，阻挡膜和未反应的金属膜，留下金属硅化物层。 元件隔离区使压缩应力作用在半导体衬底上。 阻挡膜是使半导体基板产生拉伸应力的膜，在第一热处理中形成由形成金属膜的金属元素M的单硅化物MSi构成的金属硅化物层。

    Semiconductor device and method of manufacturing same
    5.
    发明授权
    Semiconductor device and method of manufacturing same 有权
    半导体装置及其制造方法

    公开(公告)号：US08338247B2

    公开(公告)日：2012-12-25

    申请号：US12720174

    申请日：2010-03-09

    申请人： Tadashi Yamaguchi ,  Toshiaki Tsutsumi ,  Satoshi Ogino ,  Kazumasa Yonekura ,  Kenji Kawai ,  Yoshihiro Miyagawa ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Kotaro Kihara

    发明人： Tadashi Yamaguchi ,  Toshiaki Tsutsumi ,  Satoshi Ogino ,  Kazumasa Yonekura ,  Kenji Kawai ,  Yoshihiro Miyagawa ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Kotaro Kihara

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/823835 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7843

    摘要： To improve the performance of semiconductor devices. Over an n+-type semiconductor region for source/drain of an n-channel type MISFET and a first gate electrode, and over a p+-type semiconductor region for source/drain of a p-channel type MISFET and a second gate electrode, which are formed over a semiconductor substrate, a metal silicide layer including nickel platinum silicide is formed by a salicide process. After that, a tensile stress film is formed over the whole face of the semiconductor substrate, and then the tensile stress film over the p-channel type MISFET is removed by dry-etching, and, after a compression stress film is formed over the whole face of the semiconductor substrate, the compression stress film over the n-channel type MISFET is removed by dry-etching. The Pt concentration in the metal silicide layer is highest at the surface, and becomes lower as the depth from the surface increases.

    摘要翻译： 提高半导体器件的性能。 在用于n沟道型MISFET和第一栅电极的源极/漏极的n +型半导体区域上，以及用于p沟道型MISFET和第二栅电极的源极/漏极的p +型半导体区域上，其中 形成在半导体衬底上，通过自对准硅化物工艺形成包括镍铂硅化物的金属硅化物层。 之后，在半导体基板的整个面上形成拉伸应力膜，然后通过干法蚀刻去除p沟道型MISFET上的拉伸应力膜，并且在整个压电应力膜形成之后 在半导体衬底的表面上，通过干蚀刻去除n沟道型MISFET上的压缩应力膜。 金属硅化物层中的Pt浓度在表面处最高，并且随着从表面的深度增加而变低。

    Method of manufacturing a semiconductor device
    6.
    发明授权
    Method of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US08022445B2

    公开(公告)日：2011-09-20

    申请号：US12510026

    申请日：2009-07-27

    申请人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

    发明人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

    IPC分类号： H01L29/04

    CPC分类号： H01L29/045 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7848

    摘要： A method of manufacturing a semiconductor device, including the steps of preparing a silicon substrate which has a main surface whose plane direction is a surface (100); forming an n channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) which has a gate electrode, a source region, a drain region and a channel whose channel length direction is parallel to a crystal orientation of the silicon substrate; and forming NiSi over the gate electrode and NiSi2 over the source region and the drain region at the same steps.

    摘要翻译： 一种制造半导体器件的方法，包括以下步骤：制备具有平面方向为表面（100）的主表面的硅衬底; 形成具有栅电极，源极区，漏极区和沟道长度方向平行于硅衬底的晶体取向<100°的沟道的n沟道MISFET（金属绝缘体半导体场效应晶体管）; 并且在相同的步骤上在源极区域和漏极区域上在栅电极和NiSi 2上形成NiSi。

    Semiconductor device and manufacturing method thereof
    7.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US07936016B2

    公开(公告)日：2011-05-03

    申请号：US12413980

    申请日：2009-03-30

    申请人： Toshiaki Tsutsumi ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

    发明人： Toshiaki Tsutsumi ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

    IPC分类号： H01L29/76

    CPC分类号： H01L23/485 ,  H01L21/28518 ,  H01L2924/0002 ,  H01L2924/00

    摘要： There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.

    摘要翻译： 提供了具有金属硅化物层的半导体器件，其可以抑制器件的故障和功率消耗的增加。 半导体器件具有包含硅并具有主表面的半导体衬底，形成在半导体衬底的主表面中的第一和第二杂质扩散层，形成在第二杂质扩散层上的金属硅化物，以及氮化硅膜和第一 层间绝缘膜依次层叠在金属硅化物上。 在半导体器件中，形成穿过氮化硅膜和第一层间绝缘膜并到达金属硅化物表面的接触孔。 位于接触孔正下方的金属硅化物的一部分的厚度小于位于接触孔周围的金属硅化物的一部分的厚度。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20100230761A1

    公开(公告)日：2010-09-16

    申请号：US12720174

    申请日：2010-03-09

    申请人： Tadashi Yamaguchi ,  Toshiaki Tsutsumi ,  Satoshi Ogino ,  Kazumasa Yonekura ,  Kenji Kawai ,  Yoshihiro Miyagawa ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Kotaro Kihara

    发明人： Tadashi Yamaguchi ,  Toshiaki Tsutsumi ,  Satoshi Ogino ,  Kazumasa Yonekura ,  Kenji Kawai ,  Yoshihiro Miyagawa ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Kotaro Kihara

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/823835 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7843

    摘要： To improve the performance of semiconductor devices. Over an n+-type semiconductor region for source/drain of an n-channel type MISFET and a first gate electrode, and over a p+-type semiconductor region for source/drain of a p-channel type MISFET and a second gate electrode, which are formed over a semiconductor substrate, a metal silicide layer including nickel platinum silicide is formed by a salicide process. After that, a tensile stress film is formed over the whole face of the semiconductor substrate, and then the tensile stress film over the p-channel type MISFET is removed by dry-etching, and, after a compression stress film is formed over the whole face of the semiconductor substrate, the compression stress film over the n-channel type MISFET is removed by dry-etching. The Pt concentration in the metal silicide layer is highest at the surface, and becomes lower as the depth from the surface increases.

    摘要翻译： 提高半导体器件的性能。 在用于n沟道型MISFET和第一栅电极的源极/漏极的n +型半导体区域上，以及用于p沟道型MISFET和第二栅电极的源极/漏极的p +型半导体区域上，其中 形成在半导体衬底上，通过自对准硅化物工艺形成包括镍铂硅化物的金属硅化物层。 之后，在半导体基板的整个面上形成拉伸应力膜，然后通过干法蚀刻去除p沟道型MISFET上的拉伸应力膜，并且在整个压电应力膜形成之后 在半导体衬底的表面上，通过干蚀刻去除n沟道型MISFET上的压缩应力膜。 金属硅化物层中的Pt浓度在表面处最高，并且随着从表面的深度增加而变低。

    SEMICONDUCTOR DEVICE INCLUDING CMIS TRANSISTOR
    10.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING CMIS TRANSISTOR 审中-公开
    包含CMIS晶体管的半导体器件

    公开(公告)号：US20070284671A1

    公开(公告)日：2007-12-13

    申请号：US11759564

    申请日：2007-06-07

    申请人： Toshiaki TSUTSUMI ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

    发明人： Toshiaki TSUTSUMI ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

    IPC分类号： H01L29/94 ,  H01L21/8238

    CPC分类号： H01L21/823842 ,  H01L21/28097 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/66545

    摘要： Gate electrodes made of polysilicon film are isolated and face each other by way of a side wall spacer portion that fills a gap formed above an isolation insulating film at the boundary of NMIS region and PMIS region. A first metal film is formed on one of the gate electrodes, and an inhomogeneous second metal film is formed on the other of the gate electrodes. The both gate electrodes become inhomogeneous metal silicide gates through the promotion of silicide reaction by heat treatment. The mutual diffusion of metal atoms from the metal film to the gate electrode is suppressed by the interposition of the side wall spacer portion being an insulating film.

    摘要翻译： 由多晶硅膜制成的栅电极被隔离并且通过填充在NMIS区域和PMIS区域的边界处的隔离绝缘膜上形成的间隙的侧壁间隔部分相互面对。 在一个栅电极上形成第一金属膜，另一个栅电极上形成非均匀的第二金属膜。 通过热处理促进硅化物反应，两个栅电极成为不均匀的金属硅化物栅极。 通过插入作为绝缘膜的侧壁间隔物部分来抑制金属膜从金属膜到栅电极的相互扩散。