公开(公告)号：US20120188218A1

公开(公告)日：2012-07-26

申请号：US13395998

申请日：2010-06-25

申请人： Takuya Hachida ,  Yasushi Sasaki ,  Yuhichiroh Murakami ,  Shuji Nishi ,  Seijirou Gyouten

发明人： Takuya Hachida ,  Yasushi Sasaki ,  Yuhichiroh Murakami ,  Shuji Nishi ,  Seijirou Gyouten

IPC分类号： G09G3/36 ,  G06F3/038

CPC分类号： G09G3/3659 ,  G09G2300/0842 ,  G09G2330/021 ,  G09G2340/0435 ,  G09G2360/144

摘要： A memory-type liquid crystal display device includes a liquid crystal panel including memory circuits, and conducts a refresh operation more than once during a display holding period after rewriting of a screen. The memory-type liquid crystal display device increases at least one of (i) a frequency at which the screen is rewritten and (ii) a frequency at which the refresh operation is conducted during the display holding period as an intensity of light received by the liquid crystal panel increases. This allows the memory-type liquid crystal display device to reduce power consumption while keeping its display quality.

摘要翻译： 记忆型液晶显示装置包括具有存储电路的液晶面板，并且在重写画面之后的显示保持期间不止一次进行刷新动作。 记忆型液晶显示装置增加以下至少一个：（i）画面重写的频率和（ii）在显示保持期间进行刷新操作的频率，作为由 液晶面板增加。 这使得存储型液晶显示装置在保持其显示质量的同时降低功耗。

公开(公告)号：US08717273B2

公开(公告)日：2014-05-06

申请号：US13395998

申请日：2010-06-25

申请人： Takuya Hachida ,  Yasushi Sasaki ,  Yuhichiroh Murakami ,  Shuji Nishi ,  Seijirou Gyouten

发明人： Takuya Hachida ,  Yasushi Sasaki ,  Yuhichiroh Murakami ,  Shuji Nishi ,  Seijirou Gyouten

IPC分类号： G09G3/36

CPC分类号： G09G3/3659 ,  G09G2300/0842 ,  G09G2330/021 ,  G09G2340/0435 ,  G09G2360/144

摘要： A memory-type liquid crystal display device includes a liquid crystal panel including memory circuits, and conducts a refresh operation more than once during a display holding period after rewriting of a screen. The memory-type liquid crystal display device increases at least one of (i) a frequency at which the screen is rewritten and (ii) a frequency at which the refresh operation is conducted during the display holding period as an intensity of light received by the liquid crystal panel increases. This allows the memory-type liquid crystal display device to reduce power consumption while keeping its display quality.

摘要翻译： 记忆型液晶显示装置包括具有存储电路的液晶面板，并且在重写画面之后的显示保持期间不止一次进行刷新动作。 记忆型液晶显示装置增加以下至少一个：（i）画面重写的频率和（ii）在显示保持期间进行刷新操作的频率，作为由 液晶面板增加。 这使得存储型液晶显示装置在保持其显示质量的同时降低功耗。

公开(公告)号：US20130076607A1

公开(公告)日：2013-03-28

申请号：US13701885

申请日：2011-05-11

申请人： Eiji Matsuda ,  Makoto Yokoyama ,  Shuji Nishi ,  Takahiro Yamaguchi ,  Takuya Hachida ,  Seijirou Gyouten

发明人： Eiji Matsuda ,  Makoto Yokoyama ,  Shuji Nishi ,  Takahiro Yamaguchi ,  Takuya Hachida ,  Seijirou Gyouten

IPC分类号： G09G3/36

CPC分类号： G09G3/3674 ,  G09G3/3655 ,  G09G3/3666 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2330/021

摘要： A plurality of the display panels (10A and 10B) are provided on a single substrate. For each of the plurality of the display panels (10A and 10B), there are provided data signal lines (11A and 11B), scanning signal lines (12A and 12B), data signal line drive circuits (20A and 20B) which drive the respective data signal lines (11A and 11B) and scanning signal line drive circuits (30A and 30B) which drive the respective scanning signal lines (12A and 12B). This allows achievement of lower electric power consumption and greater design freedom in a display device including a plurality of display panels which are provided on a single substrate.

摘要翻译： 多个显示面板（10A和10B）设置在单个基板上。 对于多个显示面板（10A和10B）中的每一个，提供数据信号线（11A和11B），扫描信号线（12A和12B），数据信号线驱动电路（20A和20B） 数据信号线（11A和11B）和驱动各扫描信号线（12A和12B）的扫描信号线驱动电路（30A和30B）。 这允许在包括设置在单个基板上的多个显示面板的显示装置中实现更低的电力消耗和更大的设计自由度。

公开(公告)号：US20130094166A1

公开(公告)日：2013-04-18

申请号：US13701541

申请日：2011-05-11

申请人： Makoto Yokoyama ,  Eiji Matsuda ,  Takahiro Yamaguchi ,  Shuji Nishi ,  Takuya Hachida ,  Seijirou Gyouten

发明人： Makoto Yokoyama ,  Eiji Matsuda ,  Takahiro Yamaguchi ,  Shuji Nishi ,  Takuya Hachida ,  Seijirou Gyouten

IPC分类号： H05K7/02

CPC分类号： H05K7/026 ,  G02F2001/133391 ,  G02F2001/13456 ,  G09G3/3655 ,  G09G3/3666 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2330/021

摘要： A plurality of display panels (10A and 10B) are provided on a single substrate (2). Data signal lines (11A), scanning signal lines (12A), a data signal line drive circuit (20A) for driving the data signal lines (11A), and a scanning signal line drive circuit (30A) for driving the scanning signal lines (12A) are provided for the display panel (10A). Data signal lines (11B), scanning signal lines (12B), a data signal line drive circuit (20B) for driving the data signal lines (11B), and a scanning signal line drive circuit (30B) for driving the scanning signal lines (12B) are provided for the display panel (10B). Input signal lines (17A and 17B) are provided so as not intersect each other in a plan view. This allows a reduction in power consumption and an increase in flexibility in design in a display panel which includes a plurality of display panels on a single substrate.

摘要翻译： 多个显示面板（10A和10B）设置在单个基板（2）上。 数据信号线（11A），扫描信号线（12A），用于驱动数据信号线（11A）的数据信号线驱动电路（20A）和扫描信号线驱动电路（30A） 12A）用于显示面板（10A）。 数据信号线（11B），扫描信号线（12B），用于驱动数据信号线（11B）的数据信号线驱动电路（20B）和用于驱动扫描信号线的扫描信号线驱动电路（30B） 12B）用于显示面板（10B）。 输入信号线（17A，17B）在俯视图中不相交。 这允许在单个基板上包括多个显示面板的显示面板中降低功耗并提高设计灵活性。

公开(公告)号：US08970565B2

公开(公告)日：2015-03-03

申请号：US13378233

申请日：2010-03-18

申请人： Takuya Hachida ,  Yuhichiroh Murakami ,  Shige Furuta ,  Makoto Yokoyama ,  Yasushi Sasaki

发明人： Takuya Hachida ,  Yuhichiroh Murakami ,  Shige Furuta ,  Makoto Yokoyama ,  Yasushi Sasaki

IPC分类号： G06F3/038 ,  G09G3/36 ,  G11C19/28

CPC分类号： G11C19/28 ,  G09G3/3677 ,  G09G2310/063

摘要： A stage of the shift register has (i) a set-reset type flip-flop which receives an initialization signal and (ii) a signal generating circuit which receives a simultaneous selection signal and which generates an output signal by use of an output of the flip-flop. In at least one example embodiment, the output of the flip-flop becomes inactive regardless of whether a setting signal and a resetting signal are active or inactive, as long as the initialization signal is active. The initialization signal becomes active before the end of the simultaneous selection, and then becomes inactive after the end of the simultaneous selection. This makes it possible to stabilize operation of the shift register after the end of simultaneous selection of a plurality of signal lines carried out by the display driving circuit at a predetermined timing.

摘要翻译： 移位寄存器的一级具有（i）接收初始化信号的设置复位型触发器，以及（ii）接收同时选择信号并且通过使用输出信号产生输出信号的信号发生电路 拖鞋。 在至少一个示例性实施例中，只要初始化信号有效，触发器的输出就会变得无效，而不管设置信号和复位信号是有效还是无效。 初始化信号在同时选择结束之前变为有效，然后在同时选择结束后变为无效。 这使得可以在预定定时同时选择由显示驱动电路执行的多条信号线结束之后稳定移位寄存器的操作。

公开(公告)号：US20120105395A1

公开(公告)日：2012-05-03

申请号：US13378233

申请日：2010-03-18

申请人： Takuya Hachida ,  Yuhichiroh Murakami ,  Shige Furuta ,  Makoto Yokoyama ,  Yasushi Sasaki

发明人： Takuya Hachida ,  Yuhichiroh Murakami ,  Shige Furuta ,  Makoto Yokoyama ,  Yasushi Sasaki

IPC分类号： G09G3/36 ,  G06F3/038

CPC分类号： G11C19/28 ,  G09G3/3677 ,  G09G2310/063

摘要： A stage of the shift register has (i) a set-reset type flip-flop which receives an initialization signal and (ii) a signal generating circuit which receives a simultaneous selection signal and which generates an output signal by use of an output of the flip-flop. In at least one example embodiment, the output of the flip-flop becomes inactive regardless of whether a setting signal and a resetting signal are active or inactive, as long as the initialization signal is active. The initialization signal becomes active before the end of the simultaneous selection, and then becomes inactive after the end of the simultaneous selection. This makes it possible to stabilize operation of the shift register after the end of simultaneous selection of a plurality of signal lines carried out by the display driving circuit at a predetermined timing.

摘要翻译： 移位寄存器的一级具有（i）接收初始化信号的设置复位型触发器，以及（ii）接收同时选择信号并且通过使用输出信号产生输出信号的信号发生电路 拖鞋。 在至少一个示例性实施例中，只要初始化信号有效，触发器的输出就会变得无效，而不管设置信号和复位信号是有效还是无效。 初始化信号在同时选择结束之前变为有效，然后在同时选择结束后变为无效。 这使得可以在预定定时同时选择由显示驱动电路执行的多条信号线结束之后稳定移位寄存器的操作。

公开(公告)号：US09030237B2

公开(公告)日：2015-05-12

申请号：US13818693

申请日：2011-09-01

申请人： Takuya Hachida ,  Yasushi Sasaki ,  Yuhichiroh Murakami ,  Etsuo Yamamoto

发明人： Takuya Hachida ,  Yasushi Sasaki ,  Yuhichiroh Murakami ,  Etsuo Yamamoto

IPC分类号： H03B1/00 ,  H03K3/00 ,  H03K17/687 ,  G09G3/36 ,  H03K19/017 ,  H01L27/12 ,  H03K3/356

CPC分类号： H03K17/687 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0286 ,  H01L27/124 ,  H01L27/1255 ,  H03K3/356008 ,  H03K3/356026 ,  H03K19/01714

摘要： A transistor circuit includes at least one transistor, wherein at least part of a connecting portion that connects the transistor (Tr1) and a power supply line (33) is formed from a material of which a channel of the transistor (Tr1) is made. This configuration reduces a circuit area of the transistor circuit.

摘要翻译： 晶体管电路包括至少一个晶体管，其中连接晶体管（Tr1）和电源线（33）的连接部分的至少一部分由形成晶体管（Tr1）的沟道的材料形成。 该配置减小了晶体管电路的电路面积。

公开(公告)号：US20130147524A1

公开(公告)日：2013-06-13

申请号：US13818693

申请日：2011-09-01

申请人： Takuya Hachida ,  Yasushi Sasaki ,  Yuhichiroh Murakami ,  Etsuo Yamamoto

发明人： Takuya Hachida ,  Yasushi Sasaki ,  Yuhichiroh Murakami ,  Etsuo Yamamoto

IPC分类号： H03K17/687

CPC分类号： H03K17/687 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0286 ,  H01L27/124 ,  H01L27/1255 ,  H03K3/356008 ,  H03K3/356026 ,  H03K19/01714

摘要： A transistor circuit includes at least one transistor, wherein at least part of a connecting portion that connects the transistor (Tr1) and a power supply line (33) is formed from a material of which a channel of the transistor (Tr1) is made. This configuration reduces a circuit area of the transistor circuit.

摘要翻译： 晶体管电路包括至少一个晶体管，其中连接晶体管（Tr1）和电源线（33）的连接部分的至少一部分由形成晶体管（Tr1）的沟道的材料形成。 该配置减小了晶体管电路的电路面积。