摘要:
A duty pulse is formed by setting in response to a leading edge of a clock synchronized with a peak detection of a servo frame read signal by a peak detecting circuit and by resetting by a signal by which a zero-cross point of a read signal of a phase servo pattern was detected. A head position signal is formed by integrating the duty pulse. Since there is a deviation of the timings between the peak detection and the zero-cross detection, a duty ratio is measured so as to be adjusted to 50% in the on-track state of a target cylinder. The timings for a reference clock and a zero-cross detection pulse are delayed and adjusted accordingly.
摘要:
An information storage apparatus that records servo information and user data on a recording face of a recording medium wherein a track density measuring unit measures the optimal track density for a recording face corresponding to each head targeting a storage medium on which the servo information has not yet been recorded and a recording density measuring unit measures the optimal linear density for each recording face. A servo frame writing unit writes the servo information varying a track pitch to a track pitch corresponding to the optimal track density measured by the track density measuring unit and a recording frequency to a recording frequency corresponding to the optimal linear density measured by the linear density measuring unit, for each head.
摘要:
An information storage apparatus that records servo information and user data on a recording face of a recording medium wherein a track density measuring unit measures the optimal track density for a recording face corresponding to each head targeting a storage medium on which the servo information has not yet been recorded and a recording density measuring unit measures the optimal linear density for each recording face. A servo frame writing unit writes the servo information varying a track pitch to a track pitch corresponding to the optimal track density measured by the track density measuring unit and a recording frequency to a recording frequency corresponding to the optimal linear density measured by the linear density measuring unit, for each head.
摘要:
A method of controlling a magnetic disk unit. The method controls the magnetic disk unit which comprises a disk enclosure part and a printed-circuit board part. The disk enclosure part includes at least one magnetic disk, at least one magnetic head and a mechanical part for driving each magnetic disk and each magnetic head. The printed-circuit board part includes a circuit part for controlling the disk enclosure part. The method includes the steps of writing on the magnetic disk version data indicating a type of disk enclosure part after the disk enclosure part and the printed-circuit board part are assembled, and automatically setting the circuit part of the printed-circuit board part depending on the version data which is read from the magnetic disk after the magnetic disk unit is completed.
摘要:
Upon recording, a clearance control unit performs preheating by an added control value (BR) of a base heater control value B and an adjustment heater control value R and switches that to value B when it reaches a target sector to perform write. Upon reproduction, preheating is performed by the value (BR) and the value (BR) is maintained when it reaches a target sector to perform read. A correction processing unit detects contact between the head and a medium surface while increasing the value R from a predetermined initial value Ro, and sets a new calculated base heater control value B, and value Ro as the adjustment heater control value R. Write assist adjustment in which the measured adjustment heater control value R is adjusted to a heater control value that improves characteristic deterioration immediately after recording is started wherein preheating is switched to write heating is performed.
摘要:
Disclosed is a PRML regenerating apparatus for regenerating a signal read by a head from a storage medium. This PRML regenerating apparatus has a waveform equalizing circuit for waveform-equalizing the read signal, a maximum-likelihood decoder for maximum-likelihood-decoding, after obtaining a determination value by comparing the equalized output with upper and lower slice levels, this determination value and a control circuit for setting variable a distance between the upper slice level and the lower slice level of the maximum-likelihood decoder. The distance between the upper and lower slice levels can be thereby set variable in accordance with an equalization characteristic. A ternary determination circuit of the maximum-likelihood decoder is constructed of a memory for storing a correspondence table of the equalized output and the upper or lower slice level versus the determination result and the next upper or lower slice level. The ternary determination circuit can be thereby actualized with a simple configuration.
摘要:
Disclosed is a PRML regenerating apparatus for regenerating a signal read by a head from a storage medium. This PRML regenerating apparatus has a waveform equalizing circuit for waveform-equalizing the read signal, a maximum-likelihood decoder for maximum-likelihood-decoding, after obtaining a determination value by comparing the equalized output with upper and lower slice levels, this determination value and a control circuit for setting variable a distance between the upper slice level and the lower slice level of the maximum-likelihood decoder. The distance between the upper and lower slice levels can be thereby set variable in accordance with an equalization characteristic. A ternary determination circuit of the maximum-likelihood decoder is constructed of a memory for storing a correspondence table of the equalized output and the upper or lower slice level versus the determination result and the next upper or lower slice level. The ternary determination circuit can be thereby actualized with a simple configuration.
摘要:
Disclosed is a PRML regenerating apparatus for regenerating a signal read by a head from a storage medium. This PRML regenerating apparatus has a waveform equalizing circuit for waveform-equalizing the read signal, a maximum-likelihood decoder for maximum-likelihood-decoding, after obtaining a determination value by comparing the equalized output with upper and lower slice levels, this determination value and a control circuit for setting variable a distance between the upper slice level and the lower slice level of the maximum-likelihood decoder. The distance between the upper and lower slice levels can be thereby set variable in accordance with an equalization characteristic. A ternary determination circuit of the maximum-likelihood decoder is constructed of a memory for storing a correspondence table of the equalized output and the upper or lower slice level versus the determination result and the next upper or lower slice level. The ternary determination circuit can be thereby actualized with a simple configuration.
摘要:
In an electronic device having an interface circuit which operates using a fast clock source, frequency deviation of the clock source is inspected in the mounted state. The clock pulses of the fast clock source are counted in synchronization with an electronic device serving as reference, and the result is checked; or, alignment data of transfer data and overflow/underflow of the FIFO buffer are utilized; or, the count values of an internal counter and a fast clock counter are utilized, to check for frequency deviation of the fast clock source. In the state of being mounted in the device, tests can be performed of the clock sources of all units.
摘要:
In an electronic device having an interface circuit which operates using a fast clock source, frequency deviation of the clock source is inspected in the mounted state. The clock pulses of the fast clock source are counted in synchronization with an electronic device serving as reference, and the result is checked; or, alignment data of transfer data and overflow/underflow of the FIFO buffer are utilized; or, the count values of an internal counter and a fast clock counter are utilized, to check for frequency deviation of the fast clock source. In the state of being mounted in the device, tests can be performed of the clock sources of all units.