公开(公告)号：US20130242666A1

公开(公告)日：2013-09-19

申请号：US13601233

申请日：2012-08-31

申请人： Tatsuo IZUMI ,  Eietsu Takahashi

发明人： Tatsuo IZUMI ,  Eietsu Takahashi

IPC分类号： G11C16/12 ,  G11C16/08

CPC分类号： G11C16/12 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30

摘要： A first non-selected word line including a word line adjacent to a selected word line is applied with a first write pass voltage. Furthermore, a second non-selected word line which is a non-selected word line excluding the first non-selected word line is applied with a second write pass voltage smaller than a program voltage. A control circuit, in the write operation, raises the first write pass voltage toward a first target value by executing a voltage raising operation having a first voltage rise width, X times, and raises the second write pass voltage toward a second target value by executing a voltage raising operation having a second voltage rise width, Y times. The first voltage rise width is larger than the second voltage rise width, and X times is fewer than Y times.

公开(公告)号：US20120151301A1

公开(公告)日：2012-06-14

申请号：US13176030

申请日：2011-07-05

申请人： Tatsuo IZUMI ,  Mitsuhiro Noguchi

发明人： Tatsuo IZUMI ,  Mitsuhiro Noguchi

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/2909 ,  G06F11/1048 ,  H03M13/2903 ,  H03M13/3715

摘要： This memory includes: bit lines; word lines crossing the bit lines; a memory cell array including memory cells provided to correspond to intersections between the bit lines and the word lines, respectively. A sense amplifier is connected to the bit lines and detects data stored in the memory cells. A word line driver controls a voltage of the word lines. An error-correcting unit includes a first error-correcting circuit having a first error-correcting capability and a second error-correcting circuit having a second error-correcting capability. The memory cells connected to each of the word lines in the memory cell block constitute a page. The error-correcting unit drives one of or both of the first and second error-correcting circuits during a data read operation or a data write operation according to a step count which is number of times of stepping up the voltage of the word lines during the data write operation.

摘要翻译： 这个内存包括：位线; 字线穿过位线; 存储单元阵列包括分别提供以对应于位线和字线之间的交点的存储单元。 感测放大器连接到位线并检测存储在存储单元中的数据。 字线驱动器控制字线的电压。 误差校正单元包括具有第一纠错能力的第一纠错电路和具有第二纠错能力的第二纠错电路。 连接到存储器单元块中的每个字线的存储单元构成一页。 在数据读取操作或数据写入操作期间，误差校正单元驱动第一和第二纠错电路中的一个或两个，根据作为在该期间的字线的电压升高的次数的步数 数据写入操作。

公开(公告)号：US20090057814A1

公开(公告)日：2009-03-05

申请号：US12191592

申请日：2008-08-14

申请人： Tatsuo IZUMI ,  Takeshi KAMIGAICHI ,  Shinya TAKAHASHI

发明人： Tatsuo IZUMI ,  Takeshi KAMIGAICHI ,  Shinya TAKAHASHI

IPC分类号： H01L27/105

CPC分类号： H01L27/105 ,  H01L27/0207 ,  H01L27/11526 ,  H01L27/11534 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory according to an example of the invention includes active areas, and element isolation areas which isolate the active areas. The active areas and the element isolation areas are arranged alternately in a first direction. An n-th (n is odd number) active area from an endmost portion in the first direction and an (n+1)-th active area are coupled to each other at an endmost portion in a second direction perpendicular to the first direction.

摘要翻译： 根据本发明的示例的半导体存储器包括有源区域和隔离有源区域的元件隔离区域。 有源区域和元件隔离区域沿第一方向交替布置。 从第一方向最端部分的第n（n是奇数）有效区域和第（n + 1）有效区域在垂直于第一方向的第二方向上的最末端处彼此耦合。

公开(公告)号：US20130049098A1

公开(公告)日：2013-02-28

申请号：US13412999

申请日：2012-03-06

申请人： Tatsuo IZUMI ,  Tohru Ozaki

发明人： Tatsuo IZUMI ,  Tohru Ozaki

IPC分类号： H01L29/792 ,  H01L21/425

CPC分类号： H01L29/7881 ,  H01L21/764 ,  H01L27/11524 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825

摘要： In one embodiment, a nonvolatile semiconductor memory device includes a substrate, and a plurality of cell transistors, each of which includes a first insulating layer, a charge storage layer, a second insulating layer, and a control electrode successively provided on the substrate, side surfaces of the charge storage layer including inclined surfaces. The device further includes at least one insulator including a first insulator part provided on side surfaces of the cell transistors and on a top surface of the semiconductor substrate between the cell transistors, and a second insulator part continuously provided on an air gap between the cell transistors and on the cell transistors. A first distance from the top surface of the semiconductor substrate between the cell transistors to a bottom end of the air gap is greater than a thickness of the at least one insulator provided on the side surfaces of the cell transistors.

摘要翻译： 在一个实施例中，非易失性半导体存储器件包括基板和多个单元晶体管，每个单元晶体管包括依次设置在基板上的第一绝缘层，电荷存储层，第二绝缘层和控制电极 电荷存储层的表面包括倾斜表面。 该器件还包括至少一个绝缘体，其包括设置在单元晶体管的侧表面上的第一绝缘体部分和在单元晶体管之间的半导体衬底的顶表面上，以及连续地设置在单元晶体管之间的气隙上的第二绝缘体部 并在单元晶体管上。 从单元晶体管之间的半导体衬底的顶表面到气隙的底端的第一距离大于设置在单元晶体管的侧表面上的至少一个绝缘体的厚度。

公开(公告)号：US20110141821A1

公开(公告)日：2011-06-16

申请号：US13034309

申请日：2011-02-24

申请人： Tatsuo IZUMI ,  Takeshi Kamigaichi

发明人： Tatsuo IZUMI ,  Takeshi Kamigaichi

IPC分类号： G11C16/08 ,  H01L29/792

CPC分类号： H01L27/115 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582

摘要： A non-volatile semiconductor storage device includes: a substrate; a control circuit layer provided on the substrate; a support layer provided on the control circuit layer; and a memory cell array layer provided on the support layer. The memory cell array layer includes: a first lamination part having first insulation layers and first conductive layers alternately laminated therein; and a second lamination part provided on either the top or bottom surface of the respective first lamination part and laminated so as to form a second conductive layer between second insulation layers. The control circuit layer includes at least any one of: a row decoder driving word lines provided in the memory cell array layer, and a sense amplifier sensing and amplifying a signal from bit lines provided in the memory cell array layer.

摘要翻译： 非易失性半导体存储装置包括：基板; 设置在所述基板上的控制电路层; 设置在所述控制电路层上的支撑层; 以及设置在支撑层上的存储单元阵列层。 存储单元阵列层包括：第一层叠部分，其具有交替层叠在其中的第一绝缘层和第一导电层; 以及设置在相应的第一层叠部分的顶表面或底表面上并层压以在第二绝缘层之间形成第二导电层的第二层压部件。 所述控制电路层包括以下中的至少一个：行解码器驱动设置在所述存储单元阵列层中的字线，以及读出放大器，用于感测和放大来自设置在所述存储单元阵列层中的位线的信号。

公开(公告)号：US20100311210A1

公开(公告)日：2010-12-09

申请号：US12858478

申请日：2010-08-18

申请人： Tatsuo IZUMI ,  Takeshi KAMIGAICHI

发明人： Tatsuo IZUMI ,  Takeshi KAMIGAICHI

IPC分类号： H01L21/8239

CPC分类号： H01L27/115 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582

摘要： A non-volatile semiconductor storage device includes: a substrate; a control circuit layer provided on the substrate; a support layer provided on the control circuit layer; and a memory cell array layer provided on the support layer. The memory cell array layer includes: a first lamination part having first insulation layers and first conductive layers alternately laminated therein; and a second lamination part provided on either the top or bottom surface of the respective first lamination part and laminated so as to form a second conductive layer between second insulation layers. The control circuit layer includes at least any one of: a row decoder driving word lines provided in the memory cell array layer, and a sense amplifier sensing and amplifying a signal from bit lines provided in the memory cell array layer.

摘要翻译： 非易失性半导体存储装置包括：基板; 设置在所述基板上的控制电路层; 设置在所述控制电路层上的支撑层; 以及设置在支撑层上的存储单元阵列层。 存储单元阵列层包括：第一层叠部分，其具有交替层叠在其中的第一绝缘层和第一导电层; 以及设置在相应的第一层叠部分的顶表面或底表面上并层压以在第二绝缘层之间形成第二导电层的第二层压部件。 所述控制电路层包括以下中的至少一个：行解码器驱动设置在所述存储单元阵列层中的字线，以及读出放大器，用于感测和放大来自设置在所述存储单元阵列层中的位线的信号。

公开(公告)号：US20090090960A1

公开(公告)日：2009-04-09

申请号：US12245199

申请日：2008-10-03

申请人： Tatsuo IZUMI ,  Takeshi Kamigaichi

发明人： Tatsuo IZUMI ,  Takeshi Kamigaichi

IPC分类号： H01L27/115 ,  H01L21/8247

CPC分类号： H01L27/115 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582

摘要： A non-volatile semiconductor storage device includes: a substrate; a control circuit layer provided on the substrate; a support layer provided on the control circuit layer; and a memory cell array layer provided on the support layer. The memory cell array layer includes: a first lamination part having first insulation layers and first conductive layers alternately laminated therein; and a second lamination part provided on either the top or bottom surface of the respective first lamination part and laminated so as to form a second conductive layer between second insulation layers. The control circuit layer includes at least any one of: a row decoder driving word lines provided in the memory cell array layer, and a sense amplifier sensing and amplifying a signal from bit lines provided in the memory cell array layer.

摘要翻译： 非易失性半导体存储装置包括：基板; 设置在所述基板上的控制电路层; 设置在所述控制电路层上的支撑层; 以及设置在支撑层上的存储单元阵列层。 存储单元阵列层包括：第一层叠部分，其具有交替层叠在其中的第一绝缘层和第一导电层; 以及设置在相应的第一层叠部分的顶表面或底表面上并层压以在第二绝缘层之间形成第二导电层的第二层压部件。 所述控制电路层包括以下中的至少一个：行解码器驱动设置在所述存储单元阵列层中的字线，以及读出放大器，用于感测和放大来自设置在所述存储单元阵列层中的位线的信号。

公开(公告)号：US20130077402A1

公开(公告)日：2013-03-28

申请号：US13424819

申请日：2012-03-20

申请人： Tatsuo IZUMI

发明人： Tatsuo IZUMI

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/3418 ,  G11C16/3454

摘要： A non-volatile semiconductor memory device includes a plurality of cell units and a data writing unit. The cell unit includes first and second select gate transistors and a memory string including a plurality of memory cells. The data writing unit sequentially writes lower page data and upper page data corresponding to the lower page data to a selected memory cell selected in order from one close to the first select gate transistor to the second select gate transistor, and performs a first writing operation of writing the lower page data to the selected memory cell and a second writing operation of writing the upper page data to the selected memory cell after the first writing operation for n (n is an integer equal to or greater than 2) non-selected memory cells which are adjacent to a side of the selected memory cell close to the second select gate transistor.

摘要翻译： 非易失性半导体存储器件包括多个单元单元和数据写入单元。 单元单元包括第一和第二选择栅晶体管以及包括多个存储单元的存储串。 数据写入单元顺序地将与下页数据相对应的下页数据和上页数据写入到从第一选择栅极晶体管的一个到第二选择栅极晶体管的顺序选择的选定存储单元，并执行第一写入操作 将下页数据写入所选择的存储单元，以及在对n（n是等于或大于2的整数）进行第一次写入操作之后，将上部页数据写入所选存储单元的第二写入操作。 其邻近所选存储单元的靠近第二选择栅极晶体管的一侧。

公开(公告)号：US20110096604A1

公开(公告)日：2011-04-28

申请号：US12910674

申请日：2010-10-22

申请人： Tatsuo IZUMI ,  Takeshi KAMIGAICHI

发明人： Tatsuo IZUMI ,  Takeshi KAMIGAICHI

IPC分类号： G11C16/04 ,  H01L23/49 ,  H01L23/52 ,  H01L21/768

CPC分类号： G11C16/0483 ,  H01L23/5226 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a semiconductor memory device includes first and second upper-layer contact members. The upper-layer contact members are arranged alternately with the first upper-layer contact members in a first direction and shifted in a second direction orthogonal to the first direction. Plugs are formed on the second upper-layer contact members. First metal wirings are provided on the first upper-layer contact members. Second metal wirings are provided on the plugs. A height of a top surface of the plugs is higher than a top surface of the first metal wirings. A width of a bottom surface of the first metal wirings in a shorter-side direction is shorter than a width of a top surface of the first metal wirings. A width of a bottom surface of the second metal wirings in a shorter-side direction is shorter than a width of a top surface of the second metal wirings.

摘要翻译： 根据一个实施例，半导体存储器件包括第一和第二上层接触构件。 上层接触构件与第一上层接触构件沿第一方向交替布置，并且沿与第一方向正交的第二方向移位。 插塞形成在第二上层接触构件上。 第一金属配线设置在第一上层接触构件上。 插头上设有第二金属布线。 插头顶表面的高度高于第一金属布线的顶表面。 第一金属配线在短边方向上的底面的宽度比第一金属布线的顶面的宽度短。 第二金属配线在短边方向上的底面的宽度比第二金属配线的上表面的宽度短。