公开(公告)号：US07551465B2

公开(公告)日：2009-06-23

申请号：US11741462

申请日：2007-04-27

申请人： Tecla Ghilardi ,  Paolo Tessariol ,  Giorgio Servalli ,  Alessandro Grossi ,  Angelo Visconti ,  Emilio Camerlenghi

发明人： Tecla Ghilardi ,  Paolo Tessariol ,  Giorgio Servalli ,  Alessandro Grossi ,  Angelo Visconti ,  Emilio Camerlenghi

IPC分类号： G11C5/02 ,  G11C7/02

CPC分类号： G11C16/28

摘要： A reference cell layout includes a plurality of active areas, in parallel to each other, and a first contact of the active areas, and a first gate, the first contact shorting the active areas. A memory device includes the reference cell layout and a corresponding array of memory cells having active areas sized substantially identical to the active areas of the reference cell layout and plural second contacts respectively contacting the active areas of the memory cells.

摘要翻译： 参考单元布局包括彼此并联的多个有效区域和有源区域的第一接触，以及第一栅极，第一接触部使有源区域短路。 存储器件包括参考单元格布局和相应的存储器单元阵列，其存储单元阵列具有大小与参考单元布局的有效区域基本相同的有效区域，以及分别接触存储单元的有效区域的多个第二触点。

公开(公告)号：US20080266929A1

公开(公告)日：2008-10-30

申请号：US11741462

申请日：2007-04-27

申请人： Tecla Ghilardi ,  Paolo Tessariol ,  Giorgio Servalli ,  Alessandro Grossi ,  Angelo Visconti ,  Emilio Camerlenghi

发明人： Tecla Ghilardi ,  Paolo Tessariol ,  Giorgio Servalli ,  Alessandro Grossi ,  Angelo Visconti ,  Emilio Camerlenghi

IPC分类号： G11C11/00

CPC分类号： G11C16/28

摘要： A reference cell layout includes a plurality of active areas, in parallel to each other, and a first contact of the active areas, and a first gate, the first contact shorting the active areas. A memory device includes the reference cell layout and a corresponding array of memory cells having active areas sized substantially identical to the active areas of the reference cell layout and plural second contacts respectively contacting the active areas of the memory cells.

摘要翻译： 参考单元布局包括彼此并联的多个有效区域和有源区域的第一接触，以及第一栅极，第一接触部使有源区域短路。 存储器件包括参考单元格布局和相应的存储器单元阵列，其存储单元阵列具有大小与参考单元布局的有效区域基本相同的有效区域，以及分别接触存储单元的有效区域的多个第二触点。

公开(公告)号：US06903995B2

公开(公告)日：2005-06-07

申请号：US10449761

申请日：2003-05-30

申请人： Emilio Camerlenghi ,  Paolo Cappelletti ,  Tecla Ghilardi ,  Mauro Sali ,  Giorgio Servalli

发明人： Emilio Camerlenghi ,  Paolo Cappelletti ,  Tecla Ghilardi ,  Mauro Sali ,  Giorgio Servalli

IPC分类号： G11C29/00 ,  G11C29/02 ,  G11C29/50 ,  G11C8/00

CPC分类号： G11C29/006 ,  G11C16/04 ,  G11C29/02 ,  G11C29/50 ,  G11C2029/5002

摘要： An integrated non-volatile memory device may include a first matrix of memory cells organized into rows (or word lines) and columns (or bit lines), corresponding row and column decoding circuits, and read, modify and erase circuits for reading and modifying data stored in the memory cells. Furthermore, the memory device may also include a test structure including a second matrix of memory cells smaller than the first. The second memory matrix may include word line couplings each having a different contact to gate distance. That is, each coupling is aligned a different distance from its respective gate than adjacent couplings.

摘要翻译： 集成的非易失性存储器件可以包括组织成行（或字线）和列（或位线），对应的行和列解码电路的存储器单元的第一矩阵，以及用于读取和修改数据的读取，修改和擦除电路 存储在存储单元中。 此外，存储器件还可以包括测试结构，其包括小于第一存储器单元的存储器单元的第二矩阵。 第二存储器矩阵可以包括每个具有与栅极距离的不同接触的字线耦合。 也就是说，每个联轴器与相应的门相比不同于相邻联接器的距离。

公开(公告)号：US06944061B2

公开(公告)日：2005-09-13

申请号：US10724022

申请日：2003-11-26

申请人： Emilio Camerlenghi ,  Giovanni Campardo ,  Tecla Ghilardi

发明人： Emilio Camerlenghi ,  Giovanni Campardo ,  Tecla Ghilardi

IPC分类号： G11C16/34 ,  G11C16/04

CPC分类号： G11C16/3431 ,  G11C16/3404 ,  G11C16/3418

摘要： The present invention relates to a particular single cell erasing method for recovering memory cells under reading or programming disturbs in non volatile semiconductor memory electronic devices comprising cell matrix split in sectors and organized in rows, or word lines, and columns, or bit lines.This kind of memory devices generally provides the application of a sector erasing algorithm with subsequent testing phase (erase-verify); but the method according to the present invention provides a bit by bit erasing by applying to each single word line a negative voltage used during the erasing of a whole sector and on the drain terminal of each single cell a programming voltage.With this kind of selective bias it is possible to perform a single cell, or bit by bit, erasing, allowing all the cells in case under a reading or programming disturb increasing the original threshold value thereof to be recovered.

摘要翻译： 本发明涉及一种用于在非易失性半导体存储器电子器件中读取或编程干扰的存储器单元中恢复存储单元的特定单元擦除方法，该非易失性半导体存储器电子器件包括扇区中的单元矩阵分割并以行或字线，列或位线组织。 这种存储器件通常提供具有随后的测试阶段（擦除验证）的扇区擦除算法的应用; 但是根据本发明的方法通过在每个单个字线上施加在擦除整个扇区期间使用的负电压并且在每个单电池的漏极端子上施加编程电压来逐位擦除。 利用这种选择性偏置，可以执行单个单元，或逐位擦除，允许在读取或编程干扰的情况下的所有单元增加其要恢复的原始阈值。

公开(公告)号：US20080259683A1

公开(公告)日：2008-10-23

申请号：US12104118

申请日：2008-04-16

申请人： Carlo Lisi ,  Tecla Ghilardi

发明人： Carlo Lisi ,  Tecla Ghilardi

IPC分类号： G11C16/06 ,  G11C7/00

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： A method programs a memory cell comprising: an initial phase in which a continuous voltage is applied to a drain terminal of said memory cell and a suitable programming voltage signal is applied to a gate terminal thereof; a regulation phase in which a constant voltage value is applied to said gate terminal and a voltage value of said drain terminal is regulated so as to be maintained at a fixed value until a threshold voltage value of said memory cell is set at a desired threshold voltage level; and a disable phase that stops said programming and is triggered as soon as a programming current value of said memory cell goes below a reference current value, said reference current value corresponding to the attainment by the threshold voltage value of said memory cell of the desired threshold voltage value. A programming circuit is suitable for implementing this method.

摘要翻译： 一种对存储单元进行编程的方法，包括：向所述存储单元的漏极端子施加连续电压的初始相位，并将合适的编程电压信号施加到其栅极端; 其中对所述栅极端子施加恒定电压值并且调节所述漏极端子的电压值以将其保持在固定值，直到所述存储单元的阈值电压值被设置为期望的阈值电压 水平; 以及停止所述编程并且一旦所述存储器单元的编程电流值低于参考电流值就被触发的禁止阶段，所述参考电流值对应于所述存储单元的阈值电压值达到期望阈值 电压值。 编程电路适用于实现该方法。

公开(公告)号：US07656712B2

公开(公告)日：2010-02-02

申请号：US12104118

申请日：2008-04-16

申请人： Carlo Lisi ,  Tecla Ghilardi

发明人： Carlo Lisi ,  Tecla Ghilardi

IPC分类号： G11C160/06

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： A method programs a memory cell comprising: an initial phase in which a continuous voltage is applied to a drain terminal of said memory cell and a suitable programming voltage signal is applied to a gate terminal thereof; a regulation phase in which a constant voltage value is applied to said gate terminal and a voltage value of said drain terminal is regulated so as to be maintained at a fixed value until a threshold voltage value of said memory cell is set at a desired threshold voltage level; and a disable phase that stops said programming and is triggered as soon as a programming current value of said memory cell goes below a reference current value, said reference current value corresponding to the attainment by the threshold voltage value of said memory cell of the desired threshold voltage value. A programming circuit is suitable for implementing this method.

摘要翻译： 一种对存储单元进行编程的方法，包括：向所述存储单元的漏极端子施加连续电压的初始相位，并将合适的编程电压信号施加到其栅极端; 其中对所述栅极端子施加恒定电压值并且调节所述漏极端子的电压值以将其保持在固定值，直到所述存储单元的阈值电压值被设置为期望的阈值电压 水平; 以及停止所述编程并且一旦所述存储器单元的编程电流值低于参考电流值就被触发的禁止阶段，所述参考电流值对应于所述存储单元的阈值电压值达到期望阈值 电压值。 编程电路适用于实现该方法。