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1.发明申请APPARATUSES AND METHODS COMPRISING A CHANNEL REGION HAVING DIFFERENT MINORITY CARRIER LIFETIMES 有权包含不同少数携带者生存的频道区域的装置和方法公开(公告)号：US20130043505A1
公开(公告)日：2013-02-21
申请号：US13211033
申请日：2011-08-16
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/1054 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582
摘要： Apparatuses, such as memory devices, memory cell strings, and electronic systems, and methods of forming such apparatuses are shown. One such apparatus includes a channel region that has a minority carrier lifetime that is lower at one or more end portions, than in a middle portion. Other apparatuses and methods are also disclosed.
摘要翻译： 示出了诸如存储器件，存储器单元串和电子系统的装置以及形成这种装置的方法。 一种这样的装置包括在一个或多个端部处具有比在中间部分中具有较低的少数载流子寿命的沟道区域。 还公开了其它装置和方法。
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2.发明申请INTEGRATION OF RESISTORS AND CAPACITORS IN CHARGE TRAP MEMORY DEVICE FABRICATION 有权电容跟踪存储器件制造中的电阻和电容器的集成公开(公告)号：US20110248333A1
公开(公告)日：2011-10-13
申请号：US13132312
申请日：2008-12-30
申请人： Umberto M. Meotto , Paolo Tessariol
发明人： Umberto M. Meotto , Paolo Tessariol
IPC分类号： H01L29/792 , H01L21/02
CPC分类号： H01L27/115 , H01L27/105 , H01L27/1052 , H01L27/11568 , H01L27/11573
摘要： A semiconductor device structure and method to form the same. The semiconductor device structure includes a non-volatile charge trap memory device and a resistor or capacitor. A dielectric layer of a charge trap dielectric stack of the memory device is patterned to expose a portion of a first conductive layer peripheral to the memory device. A second conductive layer formed over the dielectric layer and on the exposed portion of the first conductive layer is patterned to form resistor or capacitor contacts and capacitor plates.
摘要翻译： 一种半导体器件结构及其形成方法。 半导体器件结构包括非易失性电荷陷阱存储器件和电阻器或电容器。 图案化存储器件的电荷陷阱电介质堆叠的电介质层以暴露存储器件外围的第一导电层的一部分。 形成在电介质层上和第一导电层的暴露部分上的第二导电层被图案化以形成电阻器或电容器触点和电容器板。
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公开(公告)号：US20120119280A1
公开(公告)日：2012-05-17
申请号：US12944125
申请日：2010-11-11
申请人： Paolo Tessariol
发明人： Paolo Tessariol
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/66833 , H01L27/11568 , H01L29/40117
摘要： A charge trapping non-volatile memory may be made with a charge trapping medium including a pair of dielectric layers sandwiching a metal or semimetal layer. The metal or semimetal layer may exhibit a lower energy level than either of the adjacent sandwiching charge trapping layers, creating a good electron sink and, in some embodiments, resulting in a thinner charge trapping medium.
摘要翻译： 电荷俘获非易失性存储器可以用包含夹着金属或半金属层的一对电介质层的电荷俘获介质进行。 金属或半金属层可以表现出比相邻夹层电荷捕获层中的任一个更低的能级，产生良好的电子吸收，并且在一些实施例中导致更薄的电荷捕获介质。
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公开(公告)号：US20060205136A1
公开(公告)日：2006-09-14
申请号：US11317679
申请日：2005-12-22
申请人： Paolo Tessariol , Roberto Bez , Marcello Mariani
发明人： Paolo Tessariol , Roberto Bez , Marcello Mariani
IPC分类号： H01L21/8238
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method of making a non-volatile MOS semiconductor memory device includes a formation step, in a semiconductor material substrate, of STI isolation regions (shallow trench isolation) filled by field oxide and of memory cells separated each other by said STI isolation regions. The memory cells include a gate electrode electrically isolated from said semiconductor material substrate by a first dielectric layer, and the gate electrode includes a floating gate self-aligned to the STI isolation regions. The method includes a formation phase of said floating gate exhibiting a substantially saddle shape including a concavity; the formation step of said floating gate includes a deposition step of a first conformal conductor material layer.
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公开(公告)号：US08569891B1
公开(公告)日：2013-10-29
申请号：US12724491
申请日：2010-03-16
IPC分类号： G11C11/24
CPC分类号： H01L21/76807 , H01L21/76808 , H01L21/76811 , H01L21/76816 , H01L21/7684 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/5283 , H01L27/1052 , H01L27/11521 , H01L2924/0002 , H01L2924/00
摘要： Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.
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6.发明授权Method of making a floating gate non-volatile MOS semiconductor memory device with improved capacitive coupling 有权制造具有改进的电容耦合的浮栅非易失性MOS半导体存储器件的方法公开(公告)号：US08384148B2
公开(公告)日：2013-02-26
申请号：US11317679
申请日：2005-12-22
申请人： Paolo Tessariol , Roberto Bez , Marcello Mariani
发明人： Paolo Tessariol , Roberto Bez , Marcello Mariani
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method of making a non-volatile MOS semiconductor memory device includes a formation step, in a semiconductor material substrate, of STI isolation regions (shallow trench isolation) filled by field oxide and of memory cells separated each other by said STI isolation regions. The memory cells include a gate electrode electrically isolated from said semiconductor material substrate by a first dielectric layer, and the gate electrode includes a floating gate self-aligned to the STI isolation regions. The method includes a formation phase of said floating gate exhibiting a substantially saddle shape including a concavity; the formation step of said floating gate includes a deposition step of a first conformal conductor material layer.
摘要翻译： 一种制造非易失性MOS半导体存储器件的方法包括在半导体材料衬底中形成由场氧化物填充的STI隔离区（浅沟槽隔离）和由所述STI隔离区彼此分离的存储单元的形成步骤。 存储单元包括通过第一介电层与所述半导体材料基板电隔离的栅电极，并且所述栅电极包括与所述STI隔离区自对准的浮置栅极。 该方法包括所述浮动栅极的形成阶段，其显示包括凹面的基本上鞍形; 所述浮栅的形成步骤包括第一共形导体材料层的沉积步骤。
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7.发明授权Integration of resistors and capacitors in charge trap memory device fabrication 有权在电荷陷阱存储器件制造中集成电阻和电容器公开(公告)号：US08772905B2
公开(公告)日：2014-07-08
申请号：US13132312
申请日：2008-12-30
申请人： Umberto M. Meotto , Paolo Tessariol
发明人： Umberto M. Meotto , Paolo Tessariol
IPC分类号： H01L21/00
CPC分类号： H01L27/115 , H01L27/105 , H01L27/1052 , H01L27/11568 , H01L27/11573
摘要： A semiconductor device structure and method to form the same. The semiconductor device structure includes a non-volatile charge trap memory device and a resistor or capacitor. A dielectric layer of a charge trap dielectric stack of the memory device is patterned to expose a portion of a first conductive layer peripheral to the memory device. A second conductive layer formed over the dielectric layer and on the exposed portion of the first conductive layer is patterned to form resistor or capacitor contacts and capacitor plates.
摘要翻译： 一种半导体器件结构及其形成方法。 半导体器件结构包括非易失性电荷陷阱存储器件和电阻器或电容器。 图案化存储器件的电荷陷阱电介质堆叠的电介质层以暴露存储器件外围的第一导电层的一部分。 形成在电介质层上和第一导电层的暴露部分上的第二导电层被图案化以形成电阻器或电容器触点和电容器板。
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公开(公告)号：US08329545B1
公开(公告)日：2012-12-11
申请号：US12346363
申请日：2008-12-30
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/02233 , H01L21/28282 , H01L21/76224 , H01L27/11573 , H01L29/0649 , H01L29/66833 , H01L29/792
摘要： Subject matter disclosed herein relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of fabricating a charge trap NAND flash memory device.
摘要翻译： 本文公开的主题涉及一种制造半导体集成电路器件的方法，更具体地说涉及一种制造电荷阱NAND快闪存储器件的方法。
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公开(公告)号：US07551465B2
公开(公告)日：2009-06-23
申请号：US11741462
申请日：2007-04-27
申请人： Tecla Ghilardi , Paolo Tessariol , Giorgio Servalli , Alessandro Grossi , Angelo Visconti , Emilio Camerlenghi
发明人： Tecla Ghilardi , Paolo Tessariol , Giorgio Servalli , Alessandro Grossi , Angelo Visconti , Emilio Camerlenghi
CPC分类号： G11C16/28
摘要： A reference cell layout includes a plurality of active areas, in parallel to each other, and a first contact of the active areas, and a first gate, the first contact shorting the active areas. A memory device includes the reference cell layout and a corresponding array of memory cells having active areas sized substantially identical to the active areas of the reference cell layout and plural second contacts respectively contacting the active areas of the memory cells.
摘要翻译： 参考单元布局包括彼此并联的多个有效区域和有源区域的第一接触，以及第一栅极，第一接触部使有源区域短路。 存储器件包括参考单元格布局和相应的存储器单元阵列，其存储单元阵列具有大小与参考单元布局的有效区域基本相同的有效区域，以及分别接触存储单元的有效区域的多个第二触点。
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公开(公告)号：US20190067412A1
公开(公告)日：2019-02-28
申请号：US15689735
申请日：2017-08-29
申请人： Paolo Tessariol , Qiang Tang
发明人： Paolo Tessariol , Qiang Tang
IPC分类号： H01L49/02 , H01L27/112 , H01L23/535 , H01L21/768
摘要： Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes conductive materials located in different levels of the apparatus, dielectric materials located in different levels of the apparatus, a first conductive contact, and a second conductive contact. One of the conductive materials is between two of the dielectric materials. One of the dielectric materials is between two of the conductive materials. The first conductive contact has a length extending through the conductive materials and the dielectric materials in a direction perpendicular to the levels of the apparatus. The first conductive contact is electrically separated from the conductive materials. The second conductive contact contacts a group of conductive materials of the conductive materials.
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