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1.发明授权Test structure for the measurement of contact to gate distance in non-volatile memory devices and corresponding test method 失效用于测量非易失性存储器件中接触栅极距离的测试结构和相应的测试方法公开(公告)号：US06903995B2
公开(公告)日：2005-06-07
申请号：US10449761
申请日：2003-05-30
CPC分类号： G11C29/006 , G11C16/04 , G11C29/02 , G11C29/50 , G11C2029/5002
摘要： An integrated non-volatile memory device may include a first matrix of memory cells organized into rows (or word lines) and columns (or bit lines), corresponding row and column decoding circuits, and read, modify and erase circuits for reading and modifying data stored in the memory cells. Furthermore, the memory device may also include a test structure including a second matrix of memory cells smaller than the first. The second memory matrix may include word line couplings each having a different contact to gate distance. That is, each coupling is aligned a different distance from its respective gate than adjacent couplings.
摘要翻译： 集成的非易失性存储器件可以包括组织成行（或字线）和列（或位线），对应的行和列解码电路的存储器单元的第一矩阵，以及用于读取和修改数据的读取，修改和擦除电路 存储在存储单元中。 此外，存储器件还可以包括测试结构，其包括小于第一存储器单元的存储器单元的第二矩阵。 第二存储器矩阵可以包括每个具有与栅极距离的不同接触的字线耦合。 也就是说，每个联轴器与相应的门相比不同于相邻联接器的距离。
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公开(公告)号：US20070016735A1
公开(公告)日：2007-01-18
申请号：US11432301
申请日：2006-05-10
申请人： Francesco Mastroianni , Antonino Mondello , Elena Cussotto , Massimiliano Mollichelli , Mauro Sali
发明人： Francesco Mastroianni , Antonino Mondello , Elena Cussotto , Massimiliano Mollichelli , Mauro Sali
CPC分类号： G11C16/22 , G06F12/1433 , G06F21/6209 , G06F21/79 , G06F2212/2022
摘要： A non-volatile memory device of flash type includes first memory cells for storing data, second memory cells for storing protection information of the first memory cells, and a circuit for updating the protection information that includes a circuit for writing a plurality of versions of the protection information in the second memory cells, and a circuit for identifying a current version of the protection information.
摘要翻译： 闪存类型的非易失性存储器件包括用于存储数据的第一存储器单元，用于存储第一存储器单元的保护信息的第二存储器单元，以及用于更新保护信息的电路，其包括用于写入多个版本的电路 第二存储器单元中的保护信息，以及用于识别当前版本的保护信息的电路。
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3.发明授权Negative word line voltage regulation circuit for electrically erasable semiconductor memory devices 失效用于电可擦除半导体存储器件的负字线电压调节电路
公开(公告)号：US5659502A
公开(公告)日：1997-08-19
申请号：US665862
申请日：1996-06-19
申请人： Mauro Sali , Corrado Villa , Marcello Carrera
发明人： Mauro Sali , Corrado Villa , Marcello Carrera
CPC分类号： G11C16/30
摘要： A negative word line voltage regulation circuit integratable in an electrically erasable semiconductor memory device. The circuit regulates a negative word line voltage to be supplied to word lines of the memory device during an electrical erasure of the memory device. The circuit includes an operational amplifier with a first input coupled to a reference voltage, a second input coupled to the negative word line voltage, and an output controlling a voltage regulation branch connected between an external power supply and the negative word line voltage, to provide a regulation current for regulating the negative word line voltage. The output of the operational amplifier also controls a voltage sensing branch, connected between the external power supply and the negative word line voltage, to provide a sensing signal coupled to the second input of the operational amplifier.
摘要翻译： 可在电可擦除半导体存储器件中集成的负字线电压调节电路。 电路在存储器件的电擦除期间调节要提供给存储器件的字线的负字线电压。 电路包括具有耦合到参考电压的第一输入的运算放大器，耦合到负字线电压的第二输入，以及控制连接在外部电源和负字线电压之间的电压调节支路的输出，以提供 用于调节负字线电压的调节电流。 运算放大器的输出还控制连接在外部电源和负字线电压之间的电压感测支路，以提供耦合到运算放大器的第二输入端的感测信号。
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公开(公告)号：US06480436B2
公开(公告)日：2002-11-12
申请号：US09909467
申请日：2001-07-19
IPC分类号： G11C700
CPC分类号： G11C16/30
摘要： A semiconductor memory includes a plurality of memory cells connected to one another to form a matrix of memory cells. A charge pump is connected to the matrix of memory cells. A plurality of controllable connection elements are provided, with each controllable connection element connected between an output terminal of the charge pump and a respective column line. Connected to the output of the charge pump is the series connection of a first element equivalent to a controllable connection element, and a second element equivalent to a memory cell in a predetermined biasing condition. A voltage regulator is connected between the second equivalent element and the input terminal of the charge pump for regulating the output voltage therefrom based upon a voltage present between terminals of the second equivalent element.
摘要翻译： 半导体存储器包括彼此连接以形成存储器单元矩阵的多个存储单元。 电荷泵连接到存储器单元的矩阵。 提供多个可控制的连接元件，每个可控制的连接元件连接在电荷泵的输出端和相应的列线之间。 连接到电荷泵的输出端是等效于可控制连接元件的第一元件和等同于预定偏压状态下的存储器单元的第二元件的串联连接。 电压调节器连接在第二等效元件和电荷泵的输入端之间，用于基于第二等效元件的端子之间存在的电压来调节其输出电压。
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5.发明授权Row decoding circuit for a semiconductor non-volatile electrically programmable memory and corresponding method 有权半导体非易失性电可编程存储器的行解码电路及相应的方法公开(公告)号：US06320792B1
公开(公告)日：2001-11-20
申请号：US09633334
申请日：2000-08-07
申请人： Fabio Tassan Caser , Mauro Sali , Marcello Cane
发明人： Fabio Tassan Caser , Mauro Sali , Marcello Cane
IPC分类号： G11C1606
摘要： The invention relates to a row decoding circuit for an electrically programmable and erasable semiconductor non-volatile storage device of the type which includes a matrix of memory cells laid out as cell rows and columns and is divided into sectors, said circuit being input row decode signals and supply voltages in order to drive an output stage incorporating a complementary pair of high-voltage MOS transistors of the pull-up and pull-down type, respectively, which are connected to form an output terminal connected to the rows of one sector of the matrix, characterized in that a MOS transistor of the P-channel depletion type with enhanced gate oxide is provided between the output terminal and the pull-down transistor. The control terminal of the depletion transistor forms a further input of the circuit.
摘要翻译： 本发明涉及一种用于电可编程和可擦除的半导体非易失性存储装置的行解码电路，该电路可编程和可擦除半导体非易失性存储装置包括布置为单元行和列的存储单元的矩阵，并被划分为扇区，所述电路是输入行解码信号 和电源电压，以分别驱动并入一对互补的上拉和下拉型高压MOS晶体管的输出级，所述高压MOS晶体管被连接以形成连接到所述上拉和下拉的一个扇区的行的输出端子 矩阵，其特征在于，在输出端和下拉晶体管之间提供具有增强的栅极氧化物的P沟道耗尽型的MOS晶体管。 耗尽晶体管的控制端构成电路的另一输入。
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6.发明授权Row decoding circuit for a semiconductor non-volatile electrically programmable memory and corresponding method 有权半导体非易失性电可编程存储器的行解码电路及相应的方法
公开(公告)号：US6137725A
公开(公告)日：2000-10-24
申请号：US203937
申请日：1998-12-02
申请人： Fabio Tassan Caser , Mauro Sali , Marcello Cane
发明人： Fabio Tassan Caser , Mauro Sali , Marcello Cane
摘要： The invention relates to a row decoding circuit for an electrically programmable and erasable semiconductor non-volatile storage device of the type which includes a matrix of memory cells laid out as cell rows and columns and is divided into sectors, said circuit being input row decode signals and supply voltages in order to drive an output stage incorporating a complementary pair of high-voltage MOS transistors of the pull-up and pull-down type, respectively, which are connected to form an output terminal connected to the rows of one sector of the matrix, characterized in that a MOS transistor of the P-channel depletion type with enhanced gate oxide is provided between the output terminal and the pull-down transistor. The control terminal of the depletion transistor forms a further input of the circuit.
摘要翻译： 本发明涉及一种用于电可编程和可擦除的半导体非易失性存储装置的行解码电路，该电路可编程和可擦除半导体非易失性存储装置包括布置为单元行和列的存储单元的矩阵，并被划分为扇区，所述电路是输入行解码信号 和电源电压，以分别驱动并入一对互补的上拉和下拉型高压MOS晶体管的输出级，所述高压MOS晶体管被连接以形成连接到所述上拉和下拉的一个扇区的行的输出端子 矩阵，其特征在于，在输出端和下拉晶体管之间提供具有增强的栅极氧化物的P沟道耗尽型的MOS晶体管。 耗尽晶体管的控制端构成电路的另一输入。
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公开(公告)号：US06950337B2
公开(公告)日：2005-09-27
申请号：US10719650
申请日：2003-11-21
申请人： Andrea Bellini , Mauro Sali , Alessandro Magnavacca , Carlo Lisi
发明人： Andrea Bellini , Mauro Sali , Alessandro Magnavacca , Carlo Lisi
CPC分类号： G11C16/26 , G11C16/344 , G11C2216/22
摘要： A nonvolatile memory device with simultaneous read/write has a memory array formed by a plurality of cells organized into memory banks, and a plurality of first and second sense amplifiers. The device further has a plurality of R/W selectors associated to respective sets of cells and connecting the cells of the respective sets of cells alternately to the first sense amplifiers and to the second sense amplifiers.
摘要翻译： 具有同时读/写的非易失性存储器件具有由组织到存储体中的多个单元形成的存储器阵列以及多个第一和第二读出放大器。 该装置还具有与相应的单元组相关联的多个R / W选择器，并将各组单元的单元交替地连接到第一读出放大器和第二读出放大器。
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8.发明授权Architecture for handling internal voltages in a non-volatile memory, particularly in a single-voltage supply type of dual-work flash memory 有权用于处理非易失性存储器内部电压的架构，特别是在单电源类型的双工作闪存中公开(公告)号：US06385107B1
公开(公告)日：2002-05-07
申请号：US09710067
申请日：2000-11-09
申请人： Lorenzo Bedarida , Simone Bartoli , Mauro Sali , Antonio Russo
发明人： Lorenzo Bedarida , Simone Bartoli , Mauro Sali , Antonio Russo
IPC分类号： G11C702
摘要： An architecture handles internal voltages in a non-volatile memory array which is split into at least first and second mutually independent banks. The architecture includes first and second pluralities of generators for generating at least one of the internal voltages, which are separate from each other and connected to the first and second banks, respectively, of the nonvolatile memory array; and a control system connected to the pluralities of generators to handle the correct activation of the different generators in the different conditions of the memory array operation.
摘要翻译： 架构处理非易失性存储器阵列中的内部电压，其被分成至少第一和第二相互独立的存储体。 该结构包括用于产生彼此分离并分别连接到非易失性存储器阵列的第一和第二组的内部电压中的至少一个的第一和第二多个发生器; 以及连接到多个发电机的控制系统，以在存储器阵列操作的不同条件下处理不同发电机的正确激活。
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公开(公告)号：US5724290A
公开(公告)日：1998-03-03
申请号：US774110
申请日：1996-12-24
申请人： Mauro Sali , Marcello Cane , Corrado Villa
发明人： Mauro Sali , Marcello Cane , Corrado Villa
CPC分类号： G11C16/3495 , G11C16/349 , G11C29/88
摘要： The invention relates to a programming method and device for detecting an error and inhibiting writing into a memory. The invention provides for the inclusion, in the standard programming method, of a checking step for interrupting the programming procedure and generating an error signal detecting the attempted overwriting of a "0" with a "1". The checking step of the inventive programming method provides for an initial comparison between the contents of a plurality of bits being programmed and a corresponding plurality of bits to be written in, the generation of an error signal upon detection of homolog pairs with a value of "one", and the interruption of the byte programming procedure to prevent a "1" from being written over a "0".
摘要翻译： 本发明涉及一种用于检测错误并禁止写入存储器的编程方法和装置。 本发明提供了在标准编程方法中包括用于中断编程程序的检查步骤，并且产生检测到用“1”尝试重写“0”的错误信号。 本发明的编程方法的检查步骤提供了正被编程的多个比特的内容和要写入的对应的多个比特之间的初始比较，在检测到具有值“ 一个“，并且字节编程过程的中断，以防止在”0“上写入”1“。
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10.发明授权Non-volatile memory device with burst mode reading and corresponding reading method 有权具有突发模式读取的非易失性存储器件和相应的读取方法公开(公告)号：US06854040B1
公开(公告)日：2005-02-08
申请号：US09717938
申请日：2000-11-21
申请人： Simone Bartoli , Antonino Geraci , Mauro Sali , Lorenzo Bedarida
发明人： Simone Bartoli , Antonino Geraci , Mauro Sali , Lorenzo Bedarida
CPC分类号： G11C7/1072 , G11C7/1033 , G11C7/1045
摘要： A read control circuit and a reading method for an electronic memory device integrated on a semiconductor includes a non-volatile memory matrix with associated row and column decoders connected to respective outputs of an address counter. An address transition detect (ATD) circuit detects an input transition as the memory device is being accessed, and read amplifiers and attendant registers transfer the data read from the memory matrix to the output. The read control circuit includes a detection circuit to which is input a clock signal and a logic signal to enable reading in the burst mode. A burst read mode control logic circuit is connected downstream of the detection circuit. The method includes accessing the memory matrix in a random read mode, detecting a request for access in the burst read mode, and executing the parallel reading of a plurality of memory words during a single period of time clocked by the clock signal.
摘要翻译： 集成在半导体上的电子存储装置的读取控制电路和读取方法包括具有连接到地址计数器的相应输出的相关联的行和列解码器的非易失性存储器矩阵。 地址转换检测（ATD）电路在正在访问存储器件时检测输入转换，并且读取放大器和伴随寄存器将从存储器矩阵读取的数据传送到输出。 读取控制电路包括检测电路，在该检测电路中输入时钟信号和逻辑信号，使得能够以突发模式进行读取。 突发读模式控制逻辑电路连接在检测电路的下游。 该方法包括以随机读取模式访问存储器矩阵，以突发读取模式检测访问请求，以及在由时钟信号计时的单个时间段内执行多个存储器字的并行读取。
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