公开(公告)号：US11522045B2

公开(公告)日：2022-12-06

申请号：US17188350

申请日：2021-03-01

申请人： TESSERA LLC

发明人： Injo Ok ,  Balasubramanian Pranatharthiharan ,  Soon-Cheon Seo ,  Charan V. Surisetty

IPC分类号： H01L29/06 ,  H01L21/764 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/3065 ,  H01L29/49 ,  H01L23/485 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/532 ,  H01L23/535 ,  H01L27/088 ,  H01L29/161 ,  H01L29/417

摘要： A method of forming a semiconductor structure includes forming a first middle-of-line (MOL) oxide layer and a second MOL oxide layer in the semiconductor structure. The first MOL oxide layer including multiple gate stacks formed on a substrate, and each gate stack of the gate stacks including a source/drain junction. A first nitride layer is formed over a silicide in the first MOL oxide layer. A second nitride layer is formed. Trenches are formed through the second nitride layer down to the source/drain junctions. A nitride cap of the plurality of gate stacks is selectively recessed. At least one self-aligned contact area (CA) element is formed within the first nitride layer. The first MOL oxide layer is selectively recessed. An air-gap oxide layer is deposited. The air gap oxide layer is reduced to the at least one self-aligned CA element and the first nitride layer.

公开(公告)号：USRE50174E1

公开(公告)日：2024-10-15

申请号：US17710394

申请日：2022-03-31

申请人： Tessera LLC

发明人： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Derrick Liu ,  Soon-Cheon Seo ,  Stuart A. Sieg

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/0649 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/66545

摘要： A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

公开(公告)号：US20230299134A1

公开(公告)日：2023-09-21

申请号：US17980949

申请日：2022-11-04

申请人： TESSERA LLC

发明人： Injo Ok ,  Balasubramanian Pranatharthiharan ,  Soon-Cheon Seo ,  Charan V. Surisetty

IPC分类号： H01L29/06 ,  H01L21/764 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/3065 ,  H01L29/49 ,  H01L23/485 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/532 ,  H01L23/535 ,  H01L27/088

CPC分类号： H01L29/0649 ,  H01L21/764 ,  H01L21/762 ,  H01L21/31053 ,  H01L21/32139 ,  H01L21/3065 ,  H01L29/4975 ,  H01L23/485 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76889 ,  H01L21/823475 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/535 ,  H01L27/088 ,  H01L21/76849 ,  H01L29/4991 ,  H01L29/161

摘要： A method of forming a semiconductor structure includes forming a first middle-of-line (MOL) oxide layer and a second MOL oxide layer in the semiconductor structure. The first MOL oxide layer including multiple gate stacks formed on a substrate, and each gate stack of the gate stacks including a source/drain junction. A first nitride layer is formed over a silicide in the first MOL oxide layer. A second nitride layer is formed. Trenches are formed through the second nitride layer down to the source/drain junctions. A nitride cap of the plurality of gate stacks is selectively recessed. At least one self-aligned contact area (CA) element is formed within the first nitride layer. The first MOL oxide layer is selectively recessed. An air-gap oxide layer is deposited. The air gap oxide layer is reduced to the at least one self-aligned CA element and the first nitride layer.