公开(公告)号：US11652161B2

公开(公告)日：2023-05-16

申请号：US17345339

申请日：2021-06-11

申请人： Tessera LLC

发明人： Marc A. Bergendahl ,  Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC分类号： H01L21/00 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L21/762 ,  H01L29/775 ,  H01L29/786 ,  H01L21/311 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/6681 ,  H01L21/31111 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/78696 ,  H05K999/99

摘要： A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.

公开(公告)号：USRE50174E1

公开(公告)日：2024-10-15

申请号：US17710394

申请日：2022-03-31

申请人： Tessera LLC

发明人： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Derrick Liu ,  Soon-Cheon Seo ,  Stuart A. Sieg

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/0649 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/66545

摘要： A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

公开(公告)号：US20230352480A1

公开(公告)日：2023-11-02

申请号：US18073294

申请日：2022-12-01

申请人： Tessera LLC

发明人： Marc A. Bergendahl ,  Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC分类号： H01L27/088 ,  H01L29/49 ,  H01L29/45 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/417

CPC分类号： H01L27/0886 ,  H01L29/4966 ,  H01L29/45 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/6656 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/66545 ,  H01L29/4991 ,  H01L21/76897 ,  H01L21/7682 ,  H01L27/088 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/41791 ,  H01L29/495 ,  H01L21/823418 ,  H01L2221/1063

摘要： A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.

公开(公告)号：US11699591B2

公开(公告)日：2023-07-11

申请号：US17360819

申请日：2021-06-28

申请人： Tessera LLC

发明人： Fee Li Lie ,  Dongbing Shao ,  Robert C. Wong ,  Yongan Xu

IPC分类号： H01L21/308 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H10B10/00

CPC分类号： H01L21/3086 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/31116 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/6681 ,  H01L29/66795 ,  H01L29/785 ,  H10B10/12 ,  H10B10/18

摘要： First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.

公开(公告)号：US11557589B2

公开(公告)日：2023-01-17

申请号：US16834548

申请日：2020-03-30

申请人： TESSERA LLC

发明人： Marc A. Bergendahl ,  Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC分类号： H01L21/76 ,  H01L27/088 ,  H01L29/49 ,  H01L29/45 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/417

摘要： A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.

公开(公告)号：US11978639B2

公开(公告)日：2024-05-07

申请号：US18201061

申请日：2023-05-23

申请人： Tessera LLC

发明人： Fee Li Lie ,  Dongbing Shao ,  Robert C. Wong ,  Yongan Xu

IPC分类号： H01L21/308 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

CPC分类号： H01L21/3086 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/31116 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/6681 ,  H01L29/66795 ,  H01L29/785 ,  H10B10/12 ,  H10B10/18

摘要： First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.

公开(公告)号：US20240088268A1

公开(公告)日：2024-03-14

申请号：US18133931

申请日：2023-04-12

申请人： Tessera LLC

发明人： Marc A. Bergendahl ,  Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC分类号： H01L29/66 ,  H01L21/311 ,  H01L21/762 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/6681 ,  H01L21/31111 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/78696 ,  H05K999/99

摘要： A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.

公开(公告)号：US20240079247A1

公开(公告)日：2024-03-07

申请号：US18201061

申请日：2023-05-23

申请人： Tessera LLC

发明人： Fee Li Lie ,  Dongbing Shao ,  Robert C. Wong ,  Yongan Xu

IPC分类号： H01L21/308 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC分类号： H01L21/3086 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/31116 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/6681 ,  H01L29/66795 ,  H01L29/785

摘要： First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.