Lubricant supply device
    1.
    发明授权
    Lubricant supply device 有权
    润滑油供应装置

    公开(公告)号:US06364058B1

    公开(公告)日:2002-04-02

    申请号:US09512677

    申请日:2000-02-25

    IPC分类号: F16C1700

    摘要: A lubricant supply device is to be fitted to a nut member engaging with a screw shaft through rolling members to supply lubricant to the screw shaft along with a relative rotational motion of the nut member to the screw shaft. The device comprises an application member, a lubricant storage member and a control device. The application member for applying the lubricant on the screw shaft has at least one tongue portion, which is capable of coming into contact with at least one of rolling-member running surface of the screw shaft. The number of the at least one tongue portion is identical with or larger than the number of the rolling-member running surface. The lubricant storage member supplies the lubricant to the application member. The control device controls an amount of the lubricant supplied from the lubricant storage member to the application member.

    摘要翻译: 润滑剂供给装置将被安装到通过滚动构件与螺纹轴接合的螺母构件,以将螺母件与螺杆轴的相对旋转运动一起向螺杆轴提供润滑剂。 该装置包括施加构件,润滑剂储存构件和控制装置。 用于在螺杆轴上施加润滑剂的施加构件具有至少一个舌部,其能够与螺杆轴的滚动构件运行表面中的至少一个接触。 至少一个舌部的数量等于或大于滚动件运行表面的数量。 润滑剂储存构件将润滑剂供应到施加构件。 控制装置控制从润滑剂储存构件向施加构件供给的润滑剂的量。

    Ball screw assembly
    2.
    发明授权
    Ball screw assembly 有权
    滚珠丝杠总成

    公开(公告)号:US06276225B1

    公开(公告)日:2001-08-21

    申请号:US09438961

    申请日:1999-11-12

    IPC分类号: F16H2522

    摘要: A ball screw assembly includes a screw shaft with a spiral groove, balls along the groove, a nut with the screw shaft relatively rotatable with the balls, and a seal device. A portion of each seal member is radially divided into blocks by plural slits so as to extend from one end surface directing outward in an axial direction of the nut to an axial intermediate portion of the seal member, each block having a pair of end faces, the end faces including one end face directed to a rotational direction of the nut with respect to the screw shaft when the screw shaft is screwed into the nut and another end face opposing to the other end face, this one end face being inclined so as to be gradually displaced, towards an outer peripheral side from an inner peripheral side of the seal member, in a direction reverse to the rotational direction with respect to a radial direction of the nut, and the other end face extending in this radial direction of the nut or in a direction inclined to a side reverse to the one end face with respect to the radial direction of the nut.

    摘要翻译: 滚珠丝杠组件包括具有螺旋槽的螺杆轴,沿着凹槽的球,具有与球相对旋转的螺杆的螺母和密封装置。 每个密封构件的一部分通过多个狭缝径向地划分为多个狭缝,从而在从螺母的轴向方向向外引导到密封构件的轴向中间部分的一个端面处延伸,每个块具有一对端面, 所述端面包括当所述螺杆轴旋入所述螺母中时相对于所述螺杆轴线相对于所述螺母的旋转方向的一个端面和与所述另一端面相对的另一端面,所述一个端面倾斜,以便 在与螺母的径向方向相反的旋转方向的方向上从密封构件的内周侧向外周侧逐渐移位,另一端面在螺母的径向方向上延伸 或者相对于螺母的径向相对于与该一个端面相反的一侧倾斜的方向。

    Ball screw
    3.
    发明授权
    Ball screw 失效
    滚珠丝杠

    公开(公告)号:US06571653B1

    公开(公告)日:2003-06-03

    申请号:US09806693

    申请日:2001-06-06

    IPC分类号: F16H2524

    摘要: Lubricant retaining slits (5) are formed on a pair of seal members (2) from end surfaces (2b) thereof facing inside in the axial direction of a nut (1) of a ball screw to intermediate portions of the seal members (2), and foreign bodies removing slits (6) are formed on the seal members (2) from end surfaces (2c) thereof facing outside in the axial direction of the nut (1) to intermediate portions thereof The lubricant retaining slits (5) can positively trap the lubricant invading into the gap between the seal member (2) and the screw shaft and returns the lubricant inside the nut (1). The foreign bodies removing slits (6) can remove the foreign bodies stored on the outer peripheral surface of the screw shaft and discharged outside the nut (1).

    摘要翻译: 润滑剂保持狭缝(5)从位于滚珠丝杠的螺母(1)的轴向内侧的端面(2b)的一对密封构件(2)形成在密封构件(2)的中间部分, 从密封构件(2)的螺母(1)的轴向的外侧的端面(2c)到其中间部分形成有异物(6)。润滑剂保持狭缝(5)可以是正的 捕获润滑剂侵入到密封构件(2)和螺杆轴之间的间隙中,并将润滑剂返回到螺母(1)内。 除去狭缝(6)的异物可以去除存储在螺杆轴的外周面上的异物并将其排出到螺母(1)的外部。

    Nonvolatile semiconductor memory device
    4.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号:US08854878B2

    公开(公告)日:2014-10-07

    申请号:US13603842

    申请日:2012-09-05

    申请人: Mitsuaki Honma

    发明人: Mitsuaki Honma

    摘要: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a controller. The controller is configured to perform a verify operation using a first verification voltage and a second verification voltage (first verification voltage

    摘要翻译: 根据一个实施例,非易失性半导体存储器件包括存储单元阵列和控制器。 控制器被配置为当第一值数据被存储在第一存储单元中时,使用第一验证电压和第二验证电压(第一验证电压<第二验证电压)执行验证操作。 所述控制器被配置为当所述第一存储单元的阈值电压大于或等于所述第一存储器单元的阈值电压时,基于与所述第一存储单元相邻的第二存储单元的写入数据来确定对所述第一存储器单元的写入操作是否完成或继续 第一验证电压小于第二验证电压。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
    非易失性半导体存储器件

    公开(公告)号:US20120020154A1

    公开(公告)日:2012-01-26

    申请号:US13185755

    申请日:2011-07-19

    IPC分类号: G11C16/10 G11C16/04 G11C16/06

    摘要: According to one embodiment, a nonvolatile semiconductor memory device includes memory cells storing data in a nonvolatile manner, word lines connected to the memory cells and including a first word line and a second word line which is n-th (n is an integer of 1 or more) from the first word line, and a control circuit configured to control a voltage of a word line to write data to a memory cell so that data are written in order from the first word line to the second word line. In a write sequence of the first word line, the control circuit applies a writing voltage to the second word line before writing a memory cell connected to the first word line.

    摘要翻译: 根据一个实施例,非易失性半导体存储器件包括以非易失性方式存储数据的存储单元,连接到存储单元的字线,并且包括第n字的第一字线和第二字线(n是整数1) 或更多),以及控制电路,被配置为控制字线的电压以将数据写入存储器单元,使得从第一字线到第二字线的顺序写入数据。 在第一字线的写入序列中,控制电路在写入连接到第一字线的存储单元之前,向第二字线施加写入电压。

    Semiconductor memory device capable of detecting write completion at high speed
    7.
    发明授权
    Semiconductor memory device capable of detecting write completion at high speed 有权
    能高速检测写入完成的半导体存储器件

    公开(公告)号:US08040735B2

    公开(公告)日:2011-10-18

    申请号:US12406385

    申请日:2009-03-18

    申请人: Mitsuaki Honma

    发明人: Mitsuaki Honma

    IPC分类号: G11C11/34

    摘要: A memory cell array has a plurality of memory cells arrayed in row and column directions. A plurality of sense amplifier units includes a plurality of sense amplifiers detecting write completion of each of the memory cells selected for each row. A plurality of detection units is arranged correspondingly to the sense amplifier units, and forms a transfer path for transferring potential in accordance with a detection output signal of each sense amplifier unit. The detection units detect a sense amplifier unit corresponding to a portion where the transfer path breaks off, as a sense amplifier unit including write incompletion bit.

    摘要翻译: 存储单元阵列具有以行和列方向排列的多个存储单元。 多个读出放大器单元包括多个检测放大器,用于检测为每行选择的每个存储器单元的写入完成。 多个检测单元对应于读出放大器单元布置,并且根据每个读出放大器单元的检测输出信号形成用于传送电位的传送路径。 检测单元检测对应于传送路径断开的部分的读出放大器单元作为包括写入不完整位的读出放大器单元。

    SEMICONDUCTOR MEMORY DEVICE
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号:US20090244991A1

    公开(公告)日:2009-10-01

    申请号:US12406552

    申请日:2009-03-18

    IPC分类号: G11C7/10 G11C7/00

    摘要: A semiconductor memory device comprises a first exclusive-OR circuit which compares mth N-bit first data with (m+1)th N-bit second data, a majority circuit which generates flag data to invert the second data if a comparison result of the first exclusive-OR circuit indicates that the number of mismatch bits between the first data and the second data is not less than N/2, and generates flag data to noninvert the second data if the number of mismatch bits between the first data and the second data is less than N/2, a second exclusive-OR circuit which inverts or noninverts the second data based on the flag data, a shift register which stores the flag data generated by the majority circuit, and a pad to serially output both the inverted or noninverted second data and the flag data.

    摘要翻译: 半导体存储器件包括第一异或电路,其将第N个第N数据与第(m + 1)个N位第二数据进行比较,多数电路产生标志数据以反转第二数据,如果比较结果为 第一异或电路指示第一数据和第二数据之间的失配比特数不小于N / 2,并且如果第一数据和第二异或电路之间的失配比特数不同,则生成用于非转换第二数据的标志数据 数据小于N / 2,第二异或电路基于标志数据反转或不反相第二数据,存储由多数电路产生的标志数据的移位寄存器和用于串行输出两个反相 或非反相的第二数据和标志数据。

    Nonvolatile semiconductor storage apparatus
    9.
    发明授权
    Nonvolatile semiconductor storage apparatus 有权
    非易失性半导体存储装置

    公开(公告)号:US07505315B2

    公开(公告)日:2009-03-17

    申请号:US11850252

    申请日:2007-09-05

    IPC分类号: G11C16/04

    CPC分类号: G11C11/5642 G11C16/0483

    摘要: A nonvolatile semiconductor storage apparatus comprises a memory cell array having a plurality of memory cells which are connected to word lines and to bit lines and in each of which different information of x (x is an integer equal to or larger than 3) bits is stored in association with 2x threshold voltages, the x-bit information being able to be read from each memory cell by applying a read voltage to the corresponding word line; a row decoder connected to the word lines to supply voltages to the word lines to operate the memory cells; and a sense amplifier device connected to the bit lines to read data stored in the memory cells and to hold the read data and data written to the memory cells, wherein the x-bit information corresponding to a certain threshold voltage differs from that corresponding to the adjacent threshold voltage by only 1 bit, 2x−1 of the read voltages are each set for a pair of adjacent threshold voltages, and applying any of the read voltages to the word line determines the x-bit information stored in the memory cell, and at least two read voltages are set in order to determine information for each of the x bits.

    摘要翻译: 非易失性半导体存储装置包括具有连接到字线和位线的多个存储单元的存储单元阵列,并且其中存储x(x是等于或大于3的整数)位的不同信息 与2x个阈值电压相关联,通过向对应的字线施加读取电压,能够从每个存储单元读取x位信息; 连接到字线的行解码器以向字线提供电压以操作存储器单元; 以及连接到位线的读出放大器装置,以读取存储在存储单元中的数据,并将写入的数据和数据保存在存储单元中,其中对应于一定阈值电压的x位信息不同于与 相邻的阈值电压仅为1位,读取电压的2x-1分别针对一对相邻阈值电压设定,并且将任何读取电压施加到字线确定存储在存储器单元中的x位信息,以及 设置至少两个读取电压以便确定每个x位的信息。

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号:US07349249B2

    公开(公告)日:2008-03-25

    申请号:US11389083

    申请日:2006-03-27

    IPC分类号: G11C11/34

    摘要: A semiconductor memory device includes a memory cell array with memory cells arranged therein, each memory cell storing data defined by threshold voltage thereof, wherein the memory cell array includes first and second areas; the first area stores multi-value data written with plural write steps; and the second area stores binary data defined by first and second logic states, threshold levels of which are controlled through the plural write steps adapted to the multi-value data write.

    摘要翻译: 半导体存储器件包括其中布置有存储器单元的存储单元阵列,每个存储器单元存储由其阈值电压定义的数据,其中存储单元阵列包括第一和第二区域; 第一区域存储用多个写入步骤写入的多值数据; 并且第二区域存储由第一和第二逻辑状态定义的二进制数据,其阈值级别通过适于多值数据写入的多个写入步骤来控制。