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公开(公告)号：US20110060863A1
公开(公告)日：2011-03-10
申请号：US12716547
申请日：2010-03-03
CPC分类号： G06F12/0246 , G06F3/0611 , G06F3/064 , G06F3/0679 , G06F2212/7201 , G06F2212/7205
摘要： A controller stores therein a sector address set indicating logical storage positions within a nonvolatile-memory storage area; page addresses indicating, in units of pages, physical storage positions within the nonvolatile-memory storage area; and pieces of management information each indicating whether one or more special sectors each being either a bad sector or a trimmed sector trimmed by a TRIM command are present in the corresponding page, while associating them with each other. When an access to a specified sector address is requested, the device refers to the piece of management information and judges whether any special sector is present in the page identified by the page address corresponding to the sector address. The device generates predetermined response data if the page contains one or more special sectors and accesses the nonvolatile-memory storage position corresponding to the sector address if the page contains no special sector.
摘要翻译： 控制器在其中存储指示非易失性存储器存储区域内的逻辑存储位置的扇区地址集合; 页面地址，以页为单位指示非易失性存储器存储区域内的物理存储位置; 以及各管理信息，每个管理信息指示在相应的页面中是否存在各自为坏扇区的一个或多个特殊扇区或由TRIM命令修剪的修剪扇区，同时将它们相互关联。 当请求对指定的扇区地址的访问时，设备参考管理信息，并判断由扇区地址对应的页地址所标识的页面中是否存在特殊扇区。 如果页面包含一个或多个特殊扇区，则该设备产生预定的响应数据，并且如果页面不包含特殊扇区，则访问对应于扇区地址的非易失性存储器存储位置。
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公开(公告)号：US20110202812A1
公开(公告)日：2011-08-18
申请号：US12888822
申请日：2010-09-23
IPC分类号： G06F11/14
CPC分类号： G11C29/52 , G06F11/1008 , G06F11/1068
摘要： According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written.
摘要翻译： 根据一个实施例，半导体存储器件包括要求写入数据的半导体存储器芯片。 数据具有预定单元中的一个或多个第一数据。 该装置包括写入控制器，其写入通过使用预定数量的第一数据计算出的第一数据和冗余信息，并将其用于将预定数量的第一数据中的错误校正到不同的半导体存储器芯片中; 以及存储单元，其存储相互关联的识别信息和区域指定信息。 所述识别信息将所述第一数据和所述冗余信息相关联，并且所述区域指定信息指定所述第一数据和所述冗余信息相互写入的所述半导体存储器芯片中的多个存储区域。
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公开(公告)号：US20110202578A1
公开(公告)日：2011-08-18
申请号：US12885941
申请日：2010-09-20
IPC分类号： G06F17/30
CPC分类号： G06F12/0246 , G06F2212/7205
摘要： According to one embodiment, a semiconductor memory device performs writing of data to a semiconductor memory element in response to a request to write the data with a specified logical block address from a host and performs writing of valid data to the semiconductor memory element for compaction according to a log-structured method. The semiconductor memory device adjusts a frequency of the writing response to a request from the host and a frequency of the writing for compaction according to a predetermined ratio.
摘要翻译： 根据一个实施例，半导体存储器件响应于从主机以指定的逻辑块地址写入数据的请求，执行将数据写入到半导体存储器元件，并且执行将有效数据写入半导体存储元件以进行压缩 以日志结构的方式。 半导体存储器装置根据预定的比例调整来自主机的请求的写入响应的频率和用于压缩的写入频率。
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公开(公告)号：US20100005228A1
公开(公告)日：2010-01-07
申请号：US12393654
申请日：2009-02-26
CPC分类号： G06F12/0246 , G06F11/108 , G06F2212/7208 , G06F2212/7211
摘要： A data control apparatus includes a mapping-table managing unit that manages a mapping table that is associated with a corrupted-data recovery function of recording data and error correcting code data as redundant data that is given separately from the data, distributed and stored in units of stripe blocks in the plural nonvolatile semiconductor memory devices, the mapping table containing arrangement information of the data and the error correcting code data; a determining unit that determines whether to differentiate frequencies of writing the data into the semiconductor memory devices; and a changing unit that changes the arrangement information by switching the data stored in units of the stripe blocks managed using the mapping table to differentiate the frequencies of writing the data into the semiconductor memory devices, when the determining unit determines that the frequencies of writing the data into the semiconductor memory devices are to be differentiated.
摘要翻译： 数据控制装置包括映射表管理单元，其管理与记录数据的损坏数据恢复功能和纠错码数据相关联的映射表，作为与数据分开地分配并以单元分布和存储的冗余数据 所述多个非易失性半导体存储器件中的条形块，所述映射表包含所述数据的排列信息和所述纠错码数据; 确定单元，其确定是否将写入数据的频率区分成半导体存储器件; 以及改变单元，其通过切换存储在使用映射表管理的条带块的单元中的数据来改变排列信息，以将写入数据的频率区分为半导体存储器件，当确定单元确定写入的频率 差分数据到半导体存储器件中。
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公开(公告)号：US20120072795A1
公开(公告)日：2012-03-22
申请号：US13038804
申请日：2011-03-02
IPC分类号： G06F11/267
CPC分类号： G11C16/3418 , G11C16/00 , G11C29/028
摘要： According to one embodiment, a semiconductor memory device includes a plurality of semiconductor memory chips configured to store therein information depending on an amount of accumulated charge; a plurality of parameter storage units that are provided in correspondence with the semiconductor memory chips, each of the plurality of parameter storage units being configured to store therein a parameter that defines an electrical characteristic of a signal used for writing information into or reading information from a corresponding one of the semiconductor memory chips; an error correction encoding unit configured to generate a first correction code capable of correcting an error in the information stored in a number of semiconductor memory chips no greater than a predetermined number out of the semiconductor memory chips, from the information stored in the semiconductor memory chips; and a parameter processing unit configured to change the parameters respectively corresponding to the number of semiconductor memory chips no greater than the predetermined number, and writes the parameters changed into the parameter storage units, respectively.
摘要翻译： 根据一个实施例，半导体存储器件包括多个半导体存储器芯片，其被配置为根据累积电荷的量来存储信息; 多个参数存储单元，与所述半导体存储器芯片对应地设置，所述多个参数存储单元中的每一个被配置为在其中存储定义用于将信息写入信息或从其读取信息的信号的电特性的参数 对应的一个半导体存储器芯片; 错误校正编码单元，被配置为从存储在半导体存储器芯片中的信息生成能够校正存储在半导体存储器芯片中的不大于预定数量的多个半导体存储器芯片中的信息中的误差的第一校正代码 ; 以及参数处理单元，被配置为分别对应于不大于预定数量的半导体存储器芯片的数量分别改变参数，并将改变的参数分别写入参数存储单元。
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公开(公告)号：US20120239992A1
公开(公告)日：2012-09-20
申请号：US13486718
申请日：2012-06-01
申请人： Toshikatsu HIDA , Shinichi KANNO , Hirokuni YANO , Kazuya KITSUNAI , Shigehiro ASANO , Junji YANO
发明人： Toshikatsu HIDA , Shinichi KANNO , Hirokuni YANO , Kazuya KITSUNAI , Shigehiro ASANO , Junji YANO
CPC分类号： G06F11/1412 , G06F11/1068 , G06F11/1402 , G06F12/02 , G11C16/0483 , G11C16/3418 , G11C16/3431
摘要： A method of controlling a nonvolatile semiconductor memory including a plurality of blocks, each one of the plurality of blocks being a unit of data erasing, includes determining a monitored block as a candidate for refresh operation from among the plurality of blocks based on a predetermined condition. The method includes monitoring an error count of data stored in the monitored block and not monitoring an error count of data stored in blocks excluding the monitored block among the plurality of blocks. The method also includes performing the refresh operation on data stored in the monitored block in which the error count is larger than a first threshold value.
摘要翻译： 一种控制包括多个块的非易失性半导体存储器的方法，所述多个块中的每一个是数据擦除单元，包括：基于预定条件，将所监视的块作为所述多个块中的刷新操作的候补确定 。 该方法包括监视存储在所监视的块中的数据的错误计数，并且不监视存储在多个块中的被监视块之外的块中存储的数据的错误计数。 该方法还包括对存储在监视块中的数据执行刷新操作，其中错误计数大于第一阈值。
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公开(公告)号：US20120033496A1
公开(公告)日：2012-02-09
申请号：US13271838
申请日：2011-10-12
申请人： Hirokuni YANO , Shinichi KANNO , Toshikatsu HIDA , Hidenori MATSUZAKI , Kazuya KITSUNAI , Shigehiro ASANO
发明人： Hirokuni YANO , Shinichi KANNO , Toshikatsu HIDA , Hidenori MATSUZAKI , Kazuya KITSUNAI , Shigehiro ASANO
IPC分类号： G11C14/00
CPC分类号： G06F3/0604 , G06F3/0616 , G06F3/0631 , G06F3/064 , G06F3/0656 , G06F3/0658 , G06F3/0679 , G06F3/0685 , G06F12/0246 , G06F12/0804 , G06F12/0866 , G06F2212/7201 , G06F2212/7202 , G06F2212/7203 , G06F2212/7209 , G11C11/5628
摘要： A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
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公开(公告)号：US20120072644A1
公开(公告)日：2012-03-22
申请号：US13037970
申请日：2011-03-01
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/1009 , G06F2212/7201 , G06F2212/7205
摘要： According to one embodiment, upon request from an information processor, a semiconductor storage controller writes pieces of data in predetermined units into storage locations in which no data has been written in erased areas within a semiconductor chip's storage area. A third table and a second table which is a subset thereof include physical addresses each indicating a storage location of each of pieces of the data within the semiconductor chip. The first table includes either information specifying a second table entry or information specifying a third table entry. The semiconductor storage controller records the first and the second tables into a volatile memory or records the first table into a volatile memory and the third table into a nonvolatile memory.
摘要翻译： 根据一个实施例，根据信息处理器的要求，半导体存储控制器以预定单位将多条数据写入在半导体芯片的存储区域内的擦除区域中没有数据写入的存储位置。 作为其子集的第三表和第二表包括各自表示半导体芯片内的每个数据的存储位置的物理地址。 第一表包括指定第二表条目的信息或指定第三表条目的信息。 半导体存储控制器将第一和第二表记录到易失性存储器中，或将第一表记录到易失性存储器中，将第三表记录到非易失性存储器中。
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公开(公告)号：US20120072680A1
公开(公告)日：2012-03-22
申请号：US13038845
申请日：2011-03-02
申请人： Tetsuro KIMURA , Shigehiro ASANO
发明人： Tetsuro KIMURA , Shigehiro ASANO
IPC分类号： G06F12/00
CPC分类号： G06F11/108 , G06F12/0246 , G06F2212/1036 , G06F2212/7201 , G06F2212/7208
摘要： According to one embodiment, a semiconductor memory controlling device includes a write control unit that writes a predetermined number of pieces of first data and redundant information calculated by using the predetermined number of pieces of the first data and used for correcting an error in the first data into different semiconductor storage drives, respectively; a constructing unit that constructs a storage area for storing therein a table by using driver information, the table showing an association between a logical address and a physical address of the first data and identification information for associating the predetermined number of pieces of first data with the redundant information; and a table controlling unit that stores, into the storage area, the table associated with the identification information, the physical address and the logical address of the predetermined number of pieces of the first data, and a physical address of the redundant information.
摘要翻译： 根据一个实施例，半导体存储器控制装置包括：写入控制单元，其写入预定数量的第一数据和通过使用预定数量的第一数据计算的冗余信息，并用于校正第一数据中的错误 分别进入不同的半导体存储驱动器; 构建单元，其通过使用驾驶员信息构建用于在其中存储表的存储区域，表示第一数据的逻辑地址和物理地址之间的关联的表以及用于将预定数量的第一数据与 冗余信息; 以及表控制单元，其向存储区域存储与识别信息相关联的表，预定数量的第一数据的物理地址和逻辑地址以及冗余信息的物理地址。
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公开(公告)号：US20100122071A1
公开(公告)日：2010-05-13
申请号：US12544122
申请日：2009-08-19
申请人： Takashi YOSHIKAWA , Shigehiro ASANO
发明人： Takashi YOSHIKAWA , Shigehiro ASANO
CPC分类号： G06F15/7867
摘要： A semiconductor device includes a first circuit that executes a first calculation, a second circuit that includes a first storage unit therein and executes a second calculation, a controller that outputs a first address for specifying a first execution circuit for the first calculation and a second execution circuit for the second calculation, to the first circuit and the second circuit, and controls input of data into the first circuit, and a bus that transfers a result of the first calculation executed by the first circuit to the second circuit, wherein the result of the first calculation can be conditionally used as an address for specifying the second execution circuit.
摘要翻译： 半导体器件包括执行第一计算的第一电路，包括第一存储单元并执行第二计算的第二电路，输出用于指定用于第一计算的第一执行电路的第一地址和第二执行的控制器 用于第二次计算的电路，到第一电路和第二电路，并且控制数据到第一电路的输入以及将由第一电路执行的第一次计算的结果传送到第二电路的总线，其中， 可以有条件地将第一计算用作用于指定第二执行电路的地址。
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