公开(公告)号：US07969237B2

公开(公告)日：2011-06-28

申请号：US12623794

申请日：2009-11-23

申请人： Tetsuya Fujita ,  Yousuke Hagiwara

发明人： Tetsuya Fujita ,  Yousuke Hagiwara

IPC分类号： G05F1/10

CPC分类号： H03K19/0016 ,  H03K19/00361

摘要： A semiconductor integrated circuit device includes at least one first transistor configured to control conductance between an input power line and an output power line, at least one second transistor configured to control conductance between the input power line and the output power line, a first buffer configured to supply a first control signal for driving the at least one first transistor to a first control line connected to the at least one first transistor, a second buffer configured to generate a second control signal for driving the at least one second transistor upon receipt of the first control signal supplied through the first control line and supply the second control signal to a second control line connected to the at least one second transistor, and at least one capacitor connected between the first control line and the output power line.

摘要翻译： 一种半导体集成电路器件，包括：至少一个第一晶体管，被配置为控制输入电源线与输出电源线之间的电导;至少一个第二晶体管，被配置为控制输入电力线与输出电力线之间的电导;第一缓冲器配置 提供用于驱动所述至少一个第一晶体管的第一控制信号到连接到所述至少一个第一晶体管的第一控制线;第二缓冲器，被配置为产生用于在接收到所述至少一个第一晶体管时驱动所述至少一个第二晶体管的第二控制信号 第一控制信号通过第一控制线提供并将第二控制信号提供给连接到至少一个第二晶体管的第二控制线，以及连接在第一控制线和输出电源线之间的至少一个电容器。

公开(公告)号：US20100259316A1

公开(公告)日：2010-10-14

申请号：US12623794

申请日：2009-11-23

申请人： Tetsuya Fujita ,  Yousuke Hagiwara

发明人： Tetsuya Fujita ,  Yousuke Hagiwara

IPC分类号： G05F1/10

CPC分类号： H03K19/0016 ,  H03K19/00361

摘要： A semiconductor integrated circuit device includes at least one first transistor configured to control conductance between an input power line and an output power line, at least one second transistor configured to control conductance between the input power line and the output power line, a first buffer configured to supply a first control signal for driving the at least one first transistor to a first control line connected to the at least one first transistor, a second buffer configured to generate a second control signal for driving the at least one second transistor upon receipt of the first control signal supplied through the first control line and supply the second control signal to a second control line connected to the at least one second transistor, and at least one capacitor connected between the first control line and the output power line.

摘要翻译： 一种半导体集成电路器件，包括：至少一个第一晶体管，被配置为控制输入电源线与输出电源线之间的电导;至少一个第二晶体管，被配置为控制输入电力线与输出电力线之间的电导;第一缓冲器配置 提供用于驱动所述至少一个第一晶体管的第一控制信号到连接到所述至少一个第一晶体管的第一控制线;第二缓冲器，被配置为产生用于在接收到所述至少一个第一晶体管时驱动所述至少一个第二晶体管的第二控制信号 第一控制信号通过第一控制线提供并将第二控制信号提供给连接到至少一个第二晶体管的第二控制线，以及连接在第一控制线和输出电源线之间的至少一个电容器。

公开(公告)号：US08464517B2

公开(公告)日：2013-06-18

申请号：US12736090

申请日：2008-11-27

申请人： Tetsuya Fujita

发明人： Tetsuya Fujita

IPC分类号： F01N3/00 ,  F01N3/10

CPC分类号： B01D53/9431 ,  B01D53/9495 ,  B01D2251/2062 ,  B01D2257/404 ,  F01N3/0814 ,  F01N3/103 ,  F01N3/106 ,  F01N3/2053 ,  F01N3/2066 ,  F01N3/208 ,  F01N13/009 ,  F01N2410/00 ,  F01N2410/12 ,  F01N2560/026 ,  F01N2610/02 ,  Y02A50/2345 ,  Y02T10/24

摘要： Method to reduce NOx contained in an exhaust gas by including an oxidation catalyst device and a selective reduction type NOx catalyst device, which are arranged in this order from an upstream side, and a NOx purification system. Whether a volume of NO2 adsorbed in the oxidation catalyst device increases or decreases is estimated, and a flow rate of exhaust gas which bypasses the oxidation catalyst device on a basis of the increase or decrease in the estimated volume of adsorbed NO2 is controlled. This avoids incorrect supply of ammonia.

摘要翻译： 通过包括从上游侧依次配置的氧化催化剂装置和选择还原型NOx催化剂装置来还原废气中所含的NOx的方法和NOx净化系统。 估计在氧化催化剂装置中吸附的NO 2的体积是否增加，并且控制基于吸附的NO 2的估计体积的增加或减少而绕过氧化催化剂装置的废气的流量。 这样可以避免氨的供应不正确。

公开(公告)号：US08091949B2

公开(公告)日：2012-01-10

申请号：US12746831

申请日：2008-05-27

申请人： Morihiro Toyozumi ,  Takashi Suzuki ,  Tetsuya Fujita ,  Isao Tsuji ,  Tsutomu Sakata ,  Daiki Nagayasu

发明人： Morihiro Toyozumi ,  Takashi Suzuki ,  Tetsuya Fujita ,  Isao Tsuji ,  Tsutomu Sakata ,  Daiki Nagayasu

IPC分类号： B60J7/00

CPC分类号： H02G3/0468 ,  B60R16/0215 ,  H02G11/00

摘要： In an arrangement structure for a door wire harness, the door wire harness is arranged in a door of a vehicle body and is spanned in a space between the door and the vehicle body inside a vehicle room beyond a weather strip. The door wire harness is drawn out of a space between a door inner panel and a door trim at a door side and is fixed on the door at a wire harness drawing-out position. A door side fixing position of the door wire harness is shifted from a vehicle body side fixing position of the door wire harness in a vertical direction. A spanning section of the door wire harness between the door side fixing position and the vehicle body side fixing position is sheathed by a grommet having a flexible bellows-like tube portion and made of rubber or resin. The spanning section of the door wire harness is bent in an S-shaped configuration in a space between opposed surfaces of the door and the vehicle body when the door is closed. The door wire harness is changed from the S-shaped configuration to a straight line configuration when the door is opened.

摘要翻译： 在门线束的布置结构中，门线束布置在车体的门中，并跨越在气门条之外的车厢内的车门和车身之间的空间中。 门线束从门内板和门侧的门饰板之间的空间拉出，并且在线束拉出位置处固定在门上。 门线束的门侧固定位置在门线束的车身侧固定位置沿垂直方向偏移。 门侧固定位置与车身侧固定位置之间的门线束的跨越部分由具有柔性波纹管状管部分并由橡胶或树脂制成的索环包住。 当门关闭时，门线束的跨越部分在门和车身的相对表面之间的空间中弯曲成S形构造。 当门打开时，门线束从S形配置变为直线配置。

公开(公告)号：US20100264687A1

公开(公告)日：2010-10-21

申请号：US12517628

申请日：2007-07-02

申请人： Morihiko Toyozumi ,  Isao Tsuji ,  Daiki Nagayasu ,  Tsutomu Sakata ,  Tetsuya Fujita ,  Sung-Jin Kim

发明人： Morihiko Toyozumi ,  Isao Tsuji ,  Daiki Nagayasu ,  Tsutomu Sakata ,  Tetsuya Fujita ,  Sung-Jin Kim

IPC分类号： B60J5/00

CPC分类号： B60R16/0215 ,  H02G3/0468 ,  H02G11/00

摘要： In an arranging structure of a wire harness for a door, the wire harness is spanned between a door of a motor vehicle and a vehicle body at an indoor side inside of a weather strip. The wire harness is drawn out from a space between a door inner panel and a door trim at the door side and is provided with an excess length portion that follows opening and closing operations of the door. The excess length portion is drawn out from the space when the door is opened. The excess length portion is drawn along an arcuate outer periphery of a speaker disposed in the space to be contained in the space when the door is closed.

摘要翻译： 在用于门的线束的布置结构中，线束横跨在气压条的内侧的机动车辆的门和车体之间。 线束从门内板和门侧的门饰板之间的空间拉出，并且设置有随着门的打开和关闭操作的多余长度部分。 当门打开时，多余的长度部分从空间中拉出。 当门关闭时，多余长度部分沿着设置在空间中的扬声器的弧形外周被拉伸以容纳在空间中。

公开(公告)号：US07487370B2

公开(公告)日：2009-02-03

申请号：US11216018

申请日：2005-09-01

申请人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Hiroyuki Hara ,  Tetsuya Fujita ,  Fumitoshi Hatori ,  Masataka Matsui

发明人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Hiroyuki Hara ,  Tetsuya Fujita ,  Fumitoshi Hatori ,  Masataka Matsui

IPC分类号： G06F1/00

CPC分类号： G06F1/26 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/172

摘要： According to the present invention, there is provided a semiconductor device including a power supply circuit which receives an external power supply voltage supplied, and outputs an internal power supply voltage not higher than the external power supply voltage; a system module which receives the internal power supply voltage, and performs a predetermined operation; and a performance monitor circuit which measures a processing speed of said system module when the internal power supply voltage is applied, and, on the basis of the processing speed, outputs a first control signal which requests to set the external power supply voltage at a first level, and a second control signal which requests said power supply circuit to set the internal power supply voltage at a second level. The power supply circuit outputs the internal power supply voltage having the second level on the basis of the second control signal applied thereto.

摘要翻译： 根据本发明，提供了一种半导体器件，包括：电源电路，接收所提供的外部电源电压，并输出不高于外部电源电压的内部电源电压; 接收内部电源电压并执行预定操作的系统模块; 以及性能监视电路，其在施加所述内部电源电压时测量所述系统模块的处理速度，并且基于所述处理速度，输出请求将所述外部电源电压设置为第一的第一控制信号 电平和第二控制信号，其请求所述电源电路将内部电源电压设定在第二电平。 电源电路基于施加到其上的第二控制信号输出具有第二电平的内部电源电压。

公开(公告)号：US07245177B2

公开(公告)日：2007-07-17

申请号：US10899004

申请日：2004-07-27

申请人： Tetsuya Fujita ,  Motosugu Hamada ,  Hiroyuki Hara

发明人： Tetsuya Fujita ,  Motosugu Hamada ,  Hiroyuki Hara

IPC分类号： G05F3/24

CPC分类号： G05F3/205

摘要： This disclosure concerns semiconductor integrated circuit includes a semiconductor substrate; a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other; a plurality of MOS transistors formed in the well regions; and a substrate bias generator applying substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.

摘要翻译： 本公开涉及半导体集成电路包括半导体衬底; 多个阱区，形成在所述半导体衬底的一个表面上并彼此电隔离; 形成在所述阱区中的多个MOS晶体管; 以及衬底偏置发生器，其基于实际测量的阈值电压下的MOS晶体管的工艺导出方差，将衬底偏压到各个阱区域，以使各个MOS晶体管的阈值电压与正常阈值电压一致。

公开(公告)号：US5943271A

公开(公告)日：1999-08-24

申请号：US103134

申请日：1998-06-23

申请人： Tetsuya Fujita

发明人： Tetsuya Fujita

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/408 ,  H01L21/822 ,  H01L27/04 ,  H02M3/07 ,  H03K5/13 ,  H03K5/131 ,  H03L7/093 ,  G11C16/04

CPC分类号： G11C5/146

摘要： A semiconductor integrated circuit device permitting the chip area to be as small as possible without lowering the maximum arrival voltage is provided. This semiconductor integrated circuit device includes first to n-th charge pump circuits respectively driven on the basis of clocks CLK1, CLK2 to bias semiconductor substrate or well formed at the semiconductor substrate, wherein the i-th (i=1, . . . n-1) charge pump circuit is caused to be of a structure in which the current drivability is large, but the maximum arrival voltage is low as compared to the (i+1)-th charge pump circuit.

摘要翻译： 提供了允许芯片面积尽可能小而不降低最大到达电压的半导体集成电路器件。 该半导体集成电路器件包括分别基于时钟CLK1，CLK2驱动以偏置半导体衬底或形成在半导体衬底上的阱的第一至第n电荷泵电路，其中第i（i = 1，...，n -1）电荷泵电路成为电流驱动能力大的结构，但与第（i + 1）电荷泵电路相比最大到达电压低。

公开(公告)号：US5842082A

公开(公告)日：1998-11-24

申请号：US715897

申请日：1996-09-19

申请人： Nobuo Hyakutake ,  Yoshihiro Enomoto ,  Tetsuya Fujita ,  Kazuhiro Yoshihara

发明人： Nobuo Hyakutake ,  Yoshihiro Enomoto ,  Tetsuya Fujita ,  Kazuhiro Yoshihara

IPC分类号： G03G21/00 ,  G03G15/01 ,  G03G15/14 ,  G03G15/16 ,  G03G21/10

CPC分类号： G03G15/166 ,  G03G2215/00704 ,  G03G2215/0177

摘要： An image forming apparatus which forms an image by transferring a developed image formed on an image holding member onto a transfer material by a transfer unit. The image forming apparatus is further provided with an induced-charge density suppressing unit. This induced-charge density suppressing unit suppresses the density of electric charge induced in the area of the image holding member which is opposite to an image forming member as a result of stoppage of the image forming member that is opposite to the image holding member and is electrostatically charged.

摘要翻译： 一种图像形成装置，其通过转印单元将形成在图像保持部件上的显影图像转印到转印材料上而形成图像。 图像形成装置还设置有感应电荷密度抑制单元。 该感应电荷密度抑制单元抑制由于与图像保持部件相反的图像形成部件的停止而导致与图像形成部件相反的图像保持部件的区域的电荷密度， 静电充电

公开(公告)号：US5247333A

公开(公告)日：1993-09-21

申请号：US885883

申请日：1992-05-20

申请人： Mikio Yamamoto ,  Hidekiyo Tachibana ,  Masashi Kajimoto ,  Yutaka Toyoda ,  Jun Abe ,  Masaaki Fukuhara ,  Shigeru Inaba ,  Tetsuya Fujita

发明人： Mikio Yamamoto ,  Hidekiyo Tachibana ,  Masashi Kajimoto ,  Yutaka Toyoda ,  Jun Abe ,  Masaaki Fukuhara ,  Shigeru Inaba ,  Tetsuya Fujita

IPC分类号： G03G15/06 ,  G03G15/08 ,  G03G15/09

CPC分类号： G03G15/0815 ,  G03G15/09

摘要： Disclosed is a one-component developing apparatus in which a developing agent scale-off member such as a wire member is provided parallel to the surface of the developing agent carrier so as to be in contact with or in close proximity to a developing agent carrier. A developing agent thin layer formed on the surface of the developing agent carrier which did not contribute to development in a development region comes into contact with the developing agent scale-off member so as to be forcibly scaled off of the developing agent carrier, so that the image history is erased. When the developing agent scale-off member is made to vibrate, or a bias voltage is applied between the developing agent scale-off member and the developing agent carrier, the developing agent may be scaled off more efficiently.

摘要翻译： 公开了一种单组分显影装置，其中诸如线材的显影剂去除构件平行于显影剂载体的表面设置成与显影剂载体接触或接近显影剂载体。 在显影剂载体的表面上形成的显影剂载体的显影剂载体的显影剂薄层与显影剂剥离部件接触，从而显影剂载体被强制地剥离，使得 图像历史被删除。 当使显影剂降低构件振动或者在显影剂剥离构件和显影剂载体之间施加偏压时，可以更有效地缩放显影剂。