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    Data processor having unified memory architecture providing priority memory access
    1.
    发明授权
    Data processor having unified memory architecture providing priority memory access 失效
    数据处理器具有统一的存储器架构，提供优先存储器

    公开(公告)号：US06717583B2

    公开(公告)日：2004-04-06

    申请号：US09991705

    申请日：2001-11-26

    申请人： Tetsuya Shimomura ,  Shigeru Matsuo ,  Koyo Katsura ,  Tatsuki Inuzuka ,  Yasuhiro Nakatsuka

    发明人： Tetsuya Shimomura ,  Shigeru Matsuo ,  Koyo Katsura ,  Tatsuki Inuzuka ,  Yasuhiro Nakatsuka

    IPC分类号： G06F15167

    CPC分类号： G09G5/001 ,  G06F13/1673 ,  G06F13/18 ,  G09G5/02 ,  G09G5/363 ,  G09G5/393 ,  G09G5/395 ,  G09G2340/02 ,  G09G2360/121 ,  G09G2360/125 ,  G09G2360/128

    摘要： In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.

    摘要翻译： 为了减少由于使用主存储器的一部分作为显示帧缓冲器而导致的数据处理器的处理性能的劣化，当从CPU 310产生对存储器200的访问请求时，存储器控制器400保持 一旦请求显示控制器560停止对正在执行的存储器200的访问，当已经从存储器200传送已经执行的访问的数据时，显示控制器560保持它，并且从被保持的CPU总线310传送访问请求 当CPU总线310的访问结束时，存储器控制器400重新启动在显示控制器560中停止的访问，并将保持的数据传送到显示控制器560。

    Picture processing apparatus and picture processing method
    6.
    发明授权
    Picture processing apparatus and picture processing method 有权
    图像处理装置和图像处理方法

    公开(公告)号：US06600492B1

    公开(公告)日：2003-07-29

    申请号：US09292375

    申请日：1999-04-15

    申请人： Tetsuya Shimomura ,  Shigeru Matsuo ,  Kazuyoshi Koga ,  Koyo Katsura ,  Yasuhiro Nakatsuka ,  Kazushige Yamagishi

    发明人： Tetsuya Shimomura ,  Shigeru Matsuo ,  Kazuyoshi Koga ,  Koyo Katsura ,  Yasuhiro Nakatsuka ,  Kazushige Yamagishi

    IPC分类号： G06T1500

    CPC分类号： G06T1/60

    摘要： In order to assure that a plurality of circuits such as a CPU I/F circuit, a rendering circuit, a video input circuit and a display circuit, which are each required to always complete a processing within a prescribed time, are each assured the ability to make as many accesses to a memory as required to complete the processing within the prescribed time, it is necessary to arbitrate a contention for an access to the memory through an internal bus among the circuits by employing a bus control circuit wherein priority levels assigned to the circuits to make an access to the internal bus are dynamically changed by comparing degrees of access urgency among the circuits. In this way, circuits that each have to always complete theirs processing within a prescribed time are assured the ability to make as many accesses to the memory as required to complete the processing within the prescribed time even if a plurality of such circuits do exist.

    摘要翻译： 为了确保在规定时间内需要总是完成处理的多个电路，例如CPU I / F电路，再现电路，视频输入电路和显示电路，都能确保能力 为了在规定的时间内对存储器进行尽可能多的访问以完成处理，有必要通过使用总线控制电路来通过内部总线来仲裁访问存储器的争用，其中优先级分配给 通过比较电路之间的访问紧急程度来动态地改变访问内部总线的电路。 以这种方式，每个必须总是在规定时间内完成它们的处理的电路确保了即使存在多个这样的电路，也可以在规定的时间内完成处理所需的存储器的访问的能力。

    Data processor apparatus and shading apparatus
    10.
    发明授权
    Data processor apparatus and shading apparatus 失效
    数据处理装置和遮光装置

    公开(公告)号：US06433782B1

    公开(公告)日：2002-08-13

    申请号：US08894786

    申请日：1997-08-28

    申请人： Yasuhiro Nakatsuka ,  Shigeru Matsuo ,  Jun Satoh ,  Masanori Miyoshi ,  Koyo Katsura ,  Takashi Sone

    发明人： Yasuhiro Nakatsuka ,  Shigeru Matsuo ,  Jun Satoh ,  Masanori Miyoshi ,  Koyo Katsura ,  Takashi Sone

    IPC分类号： G06T1550

    CPC分类号： G06T1/60 ,  G06T11/40 ,  G06T15/50 ,  G06T15/80

    摘要： In a data processor and a shading apparatus used in the data processor, the data processor selects an address based on the information of a memory or a translation look-aside buffer. Therefore, even when the same data are accessed, a different address at high speed is adopted according to the hardware, object to be processed, processing, etc. A plurality of geometric vectors are given as the parameters for the vertexes of a picture, the vectors are interpolated in the picture, and the luminance of each small area in the figure is calculated using the vectors generated by the interpolation. Therefore, a spotlight or highlight can be expressed with high accuracy and at high speed even when the amount of the hardware and the extent of the picture are small.

    摘要翻译： 在数据处理器中使用的数据处理器和着色装置中，数据处理器根据存储器或翻译后备缓冲器的信息来选择一个地址。 因此，即使在访问相同的数据的情况下，也可以根据硬件，被处理对象，处理等来采用高速的不同的地址。作为图像的顶点的参数，给出多个几何矢量， 矢量被内插在图像中，并且使用通过内插生成的矢量来计算图中每个小区域的亮度。 因此，即使当硬件的数量和图像的程度小时，也可以高精度和高速度地表现聚光灯或高光。