公开(公告)号：US06717842B2

公开(公告)日：2004-04-06

申请号：US10339324

申请日：2003-01-10

申请人： Tetsuya Watanabe ,  Koji Nii ,  Yasunobu Nakase

发明人： Tetsuya Watanabe ,  Koji Nii ,  Yasunobu Nakase

IPC分类号： G11C1100

CPC分类号： G11C11/419

摘要： The dummy cell of the SRAM corresponds to a normal memory cell of which first and second P-channel MOS transistors for loading are replaced by the first and the second N-channel MOS transistors, of which gate and source are provided with power supply potential and ground potential, respectively. When a word line rises to “H” level, third and fourth N-channel MOS transistors for accessing are rendered conductive, to pass current from dummy bit line to a line of ground potential via the third N-channel MOS transistor, the first N-channel MOS transistor, and a fifth N-channel MOS transistor for driving. Accordingly, speed of potential decrease of the dummy bit line may be faster than that of bit line. Hence, operational timing can easily be optimized, and operational margin can be increased.

摘要翻译： SRAM的虚拟单元对应于其第一和第二P沟道MOS晶体管用于加载的第一和第二N沟道MOS晶体管被替代的正常存储单元，其中栅极和源极被提供有电源电位， 地电位。 当字线上升到“H”电平时，用于访问的第三和第四N沟道MOS晶体管导通，经由第三N沟道MOS晶体管将电流从虚拟位线传递到地电位，第一N 沟道MOS晶体管和用于驱动的​​第五N沟道MOS晶体管。 因此，虚拟位线的潜在降低速度可能比位线的速度更快。 因此，可以容易地优化操作时间，并且可以增加操作裕量。

公开(公告)号：US06690608B2

公开(公告)日：2004-02-10

申请号：US10329355

申请日：2002-12-27

申请人： Koji Nii ,  Yasunobu Nakase

发明人： Koji Nii ,  Yasunobu Nakase

IPC分类号： G11C702

CPC分类号： G11C7/227 ,  G11C7/22 ,  G11C29/023 ,  G11C29/026 ,  G11C29/028 ,  G11C29/24 ,  G11C2207/2281 ,  G11C2207/229

摘要： Dummy cells each having the same layout as a normal memory cell are aligned in a row direction to the normal memory cells, and are arranged in rows and columns. In each dummy cell column, a dummy bit line is arranged, and a plurality of dummy cells are simultaneously selected and connected to the corresponding dummy bit line when one word line is selected. A voltage detecting circuit detects the potentials on the dummy bit lines to determine timing of activation of a sense amplifier. In the semiconductor memory device, the potential on the dummy bit line can be changed at high speed, and internal data read timing can be optimized independent of a structure of a memory cell array.

摘要翻译： 每个具有与正常存储器单元相同布局的虚拟单元在行方向上与正常存储器单元对齐，并且被排列成行和列。 在每个虚拟单元列中，布置虚拟位线，并且当选择一个字线时，多个虚拟单元同时选择并连接到相应的虚拟位线。 电压检测电路检测虚拟位线上的电位以确定读出放大器的激活时序。 在半导体存储器件中，可以高速地改变虚拟位线上的电位，并且能够独立于存储单元阵列的结构来优化内部数据读取定时。

公开(公告)号：US06760269B2

公开(公告)日：2004-07-06

申请号：US10445009

申请日：2003-05-27

申请人： Yasunobu Nakase ,  Koji Nii

发明人： Yasunobu Nakase ,  Koji Nii

IPC分类号： G11C700

CPC分类号： G11C7/227 ,  G11C7/22 ,  G11C29/023 ,  G11C29/026 ,  G11C29/028 ,  G11C29/24 ,  G11C2207/2281

摘要： Dummy cells are divided into a plurality of divided dummy columns, and divided dummy bit lines are arranged corresponding to the divided dummy columns. These divided dummy bit lines are provided with dummy sense amplifiers that drive a sense control line transmitting a sense enable signal activating a sense amplifier. A faster activation timing of the sense amplifier can be achieved.

摘要翻译： 虚拟单元被分成多个划分的虚拟列，并且分割的虚拟位线对应于分割的虚拟列排列。 这些分开的虚拟位线设置有虚拟读出放大器，其驱动感测控制线传输感测使能信号来激活读出放大器。 可以实现读出放大器的更快的激活定时。

公开(公告)号：US08441843B2

公开(公告)日：2013-05-14

申请号：US13317846

申请日：2011-10-31

申请人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

发明人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C5/063 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

摘要： The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

公开(公告)号：US08363456B2

公开(公告)日：2013-01-29

申请号：US12975400

申请日：2010-12-22

申请人： Koji Nii

发明人： Koji Nii

IPC分类号： G11C11/00

CPC分类号： G11C11/4125

摘要： To improve reliability of a semiconductor device having an SRAM.The semiconductor device has a memory cell including six n-channel type transistors and two p-channel type transistors formed over a silicon substrate. Over the silicon substrate, a first p well, a first n well, a second p well, a second n well, and a third p well are arranged in this order when viewed in a row direction. First and second positive-phase access transistors are disposed in the first p well, first and second driver transistors are disposed in the second p well, and first and second negative-phase access transistors are arranged in the third p well.

摘要翻译： 为了提高具有SRAM的半导体器件的可靠性。 半导体器件具有包括六个n沟道型晶体管和形成在硅衬底上的两个p沟道型晶体管的存储单元。 在硅衬底上，当沿行方向观察时，以该顺序布置第一p阱，第一n阱，第二p阱，第二n阱和第三p阱。 第一和第二正相存取晶体管设置在第一p阱中，第一和第二驱动晶体管设置在第二p阱中，第一和第二负相存取晶体管被布置在第三p阱中。

公开(公告)号：US08310883B2

公开(公告)日：2012-11-13

申请号：US13193258

申请日：2011-07-28

申请人： Makoto Yabuuchi ,  Koji Nii

发明人： Makoto Yabuuchi ,  Koji Nii

IPC分类号： G11C7/00

CPC分类号： G11C8/08 ,  G11C5/147 ,  G11C11/412 ,  G11C11/413

摘要： A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.

摘要翻译： 降低电源电压的驱动器电源电路被布置在字线驱动器的电源节点处。 驱动器电源电路包括N +掺杂多晶硅的非硅化物电阻元件和降低驱动器电源节点的电压电平的下拉电路。 下拉电路包括具有与下拉驱动器电源节点的电压电平的存储单元晶体管相同的阈值电压特性的下拉晶体管，以及至少调节下拉电路的栅极电压的栅极控制电路 晶体管。 栅极控制电路以与存储单元晶体管的阈值电压的变化相关联的方式校正下拉晶体管的栅极电位。

公开(公告)号：US08072799B2

公开(公告)日：2011-12-06

申请号：US12662029

申请日：2010-03-29

申请人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

发明人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C5/063 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

摘要： The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

摘要翻译： 本发明提供了一种具有SRAM的半导体集成电路器件，其满足对具有低电源电压的SNM和写入裕度两者的要求。 半导体集成电路装置包括：与多个字线和多个互补位线对应地设置的多个静态存储单元; 多个存储单元电源线，其各自向连接到多个互补位线的多个存储器单元中的每一个提供工作电压; 多个电源电路由电阻单元构成，每个电阻单元各自向存储单元电源线提供电源电压; 以及预充电电路，其向互补位线提供与电源电压相对应的预充电电压，其中使存储单元电源线具有耦合电容，从而在相应的互补位线上传输写信号。

公开(公告)号：US07876625B2

公开(公告)日：2011-01-25

申请号：US12555447

申请日：2009-09-08

申请人： Makoto Yabuuchi ,  Koji Nii

发明人： Makoto Yabuuchi ,  Koji Nii

IPC分类号： G11C7/00

CPC分类号： G11C8/08 ,  G11C5/147 ,  G11C11/412 ,  G11C11/413

摘要： A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.

公开(公告)号：US07599214B2

公开(公告)日：2009-10-06

申请号：US12325820

申请日：2008-12-01

申请人： Koji Nii

发明人： Koji Nii

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C5/14 ,  H01L27/11 ,  H01L27/1104

摘要： Source contacts of driver transistors are short-circuited through the use of an internal metal line within a memory cell. This metal line is isolated from memory cells in an adjacent column and extends in a zigzag form in a direction of the columns of memory cells. Individual lines for transmitting the source voltage of driver transistors can be provided for each column, and the source voltage of driver transistors can be adjusted also in units of memory cell columns in the structure of single port memory cell.

摘要翻译： 驱动晶体管的源触点通过使用存储单元内的内部金属线短路。 该金属线与相邻列中的存储单元隔离，并以Z字形形式沿着存储单元列的方向延伸。 可以为每列提供用于传输驱动晶体管的源电压的单独线路，并且也可以以单端口存储器单元的结构中的存储单元列为单位来调节驱动晶体管的源极电压。

公开(公告)号：US07570540B2

公开(公告)日：2009-08-04

申请号：US12219350

申请日：2008-07-21

申请人： Koji Nii

发明人： Koji Nii

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C8/16 ,  G11C11/413

摘要： In the same row access, a voltage level of word lines WLA and WLB is set to a power supply voltage VDD-Vtp. On the other hand, in different rows access, a voltage level of word line WLA or WLB is set to power supply voltage VDD. Therefore, when both ports PA and PB simultaneously access the same row, the voltage level of word lines WLA, WLB is set to power supply voltage VDD-Vtp. Thus, a driving current amount of a memory cell is reduced, thereby preventing a reduction in a current ratio of a transistor. As a result, deterioration of SNM can be prevented.

摘要翻译： 在同一行访问中，字线WLA和WLB的电压电平被设置为电源电压VDD-Vtp。 另一方面，在不同的行访问中，字线WLA或WLB的电压电平被设置为电源电压VDD。 因此，当两个端口PA和PB同时访问同一行时，字线WLA，WLB的电压电平被设置为电源电压VDD-Vtp。 因此，减小了存储单元的驱动电流量，从而防止了晶体管的电流比的降低。 结果，可以防止SNM的劣化。