公开(公告)号：US20170147423A9

公开(公告)日：2017-05-25

申请号：US14602933

申请日：2015-01-22

Applicant: Texas Instruments Incorporated

Inventor： Yanyang Xiao ,  Alexandre Pierre Palus ,  Karl Friedrich Greb ,  Kevin Patrick Lavery ,  Paul Krause

IPC: G06F11/07

CPC classification number: G06F11/0763 ,  G06F9/3004 ,  G06F9/30076 ,  G06F11/1008 ,  G06F11/1016 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1641 ,  G06F11/1654 ,  G06F11/28 ,  G06F13/4013 ,  G06K9/00986 ,  G11C29/00 ,  G11C29/14 ,  G11C29/48 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/13 ,  H03M13/27

Abstract: An electronic circuit includes a microcontroller processor (410), a peripheral (420) coupled with the processor, an endian circuit (470) coupled with the processor and the peripheral to selectively provide different endianess modes of operation, and a detection circuit (140) to detect a failure to select a given endianess, whereby inadvertent switch of endianess due to faults is avoided. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.

公开(公告)号：US10430205B2

公开(公告)日：2019-10-01

申请号：US15225342

申请日：2016-08-01

Applicant: Texas Instruments Incorporated

Inventor： Alexandre Pierre Palus

IPC: G06F9/445 ,  G06F9/38 ,  G06F11/16 ,  G06F13/24

Abstract: An embodiment of the invention provides a method for changing a multi-processor system from a performance mode to a safety mode while the system continues to run software. When an external event or exception occurs, context is switched from the performance mode to the safety mode. After context is switched, at least one pair of CPUs is synchronized to operate in the safety mode. In addition, a multi-processor system may be switched form the safety mode to the performance mode while the software continues to operate.

公开(公告)号：US09710318B2

公开(公告)日：2017-07-18

申请号：US14602933

申请日：2015-01-22

Applicant: Texas Instruments Incorporated

Inventor： Yanyang Xiao ,  Alexandre Pierre Palus ,  Karl Friedrich Greb ,  Kevin Patrick Lavery ,  Paul Krause

IPC: G06F11/07 ,  G11C29/52 ,  G11C29/00 ,  G11C29/48 ,  G06F11/10 ,  G11C29/14 ,  H03M13/27 ,  G06F13/40 ,  G06K9/00 ,  G06F9/30 ,  G06F11/28 ,  G06F11/16 ,  H03M13/13 ,  G11C29/04

CPC classification number: G06F11/0763 ,  G06F9/3004 ,  G06F9/30076 ,  G06F11/1008 ,  G06F11/1016 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1641 ,  G06F11/1654 ,  G06F11/28 ,  G06F13/4013 ,  G06K9/00986 ,  G11C29/00 ,  G11C29/14 ,  G11C29/48 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/13 ,  H03M13/27

Abstract: An electronic circuit includes a microcontroller processor (410), a peripheral (420) coupled with the processor, an endian circuit (470) coupled with the processor and the peripheral to selectively provide different endianess modes of operation, and a detection circuit (140) to detect a failure to select a given endianess, whereby inadvertent switch of endianess due to faults is avoided. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.

公开(公告)号：US20150143181A1

公开(公告)日：2015-05-21

申请号：US14602933

申请日：2015-01-22

Applicant: Texas Instruments Incorporated

Inventor： Yanyang Xiao ,  Alexandre Pierre Palus ,  Karl Friedrich Greb ,  Kevin Patrick Lavery ,  Paul Krause

IPC: G06F11/07

CPC classification number: G06F11/0763 ,  G06F9/3004 ,  G06F9/30076 ,  G06F11/1008 ,  G06F11/1016 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1641 ,  G06F11/1654 ,  G06F11/28 ,  G06F13/4013 ,  G06K9/00986 ,  G11C29/00 ,  G11C29/14 ,  G11C29/48 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/13 ,  H03M13/27

Abstract: An electronic circuit includes a microcontroller processor (410), a peripheral (420) coupled with the processor, an endian circuit (470) coupled with the processor and the peripheral to selectively provide different endianess modes of operation, and a detection circuit (140) to detect a failure to select a given endianess, whereby inadvertent switch of endianess due to faults is avoided. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.

Abstract translation: 电子电路包括微处理器（410），与处理器耦合的外围设备（420），与处理器和外围设备耦合的端电路（470），以选择性地提供不同的端对端操作模式;以及检测电路（140） 检测到无法选择给定的字节码，从而避免了由于故障导致的无意识切换。 还公开了其它电路，装置，系统，操作方法和制造方法。

公开(公告)号：US20160335103A1

公开(公告)日：2016-11-17

申请号：US15225342

申请日：2016-08-01

Applicant: Texas Instruments Incorporated

Inventor： Alexandre Pierre Palus

IPC: G06F9/445 ,  G06F9/38 ,  G06F13/24

CPC classification number: G06F9/44505 ,  G06F9/38 ,  G06F9/3861 ,  G06F11/1641 ,  G06F11/1658 ,  G06F11/1675 ,  G06F13/24 ,  G06F2201/845

Abstract: An embodiment of the invention provides a method for changing a multi-processor system from a performance mode to a safety mode while the system continues to run software. When an external event or exception occurs, context is switched from the performance mode to the safety mode. After context is switched, at least one pair of CPUs is synchronized to operate in the safety mode. In addition, a multi-processor system may be switched form the safety mode to the performance mode while the software continues to operate.

Abstract translation: 本发明的实施例提供了一种在系统继续运行软件时将多处理器系统从性能模式改变为安全模式的方法。 当外部事件或异常发生时，上下文从性能模式切换到安全模式。 在上下文切换之后，至少一对CPU被同步以在安全模式下操作。 此外，当软件继续运行时，多处理器系统可以从安全模式切换到性能模式。