公开(公告)号：US20150171158A1

公开(公告)日：2015-06-18

申请号：US14569975

申请日：2014-12-15

Applicant: Texas Instruments Incorporated

Inventor： Greg Charles BALDWIN ,  Kamel BENAISSA ,  Sarah LIU ,  Song Zhao

IPC: H01L49/02 ,  H01L21/265 ,  H01L21/8238

CPC classification number: H01L28/22 ,  G06F17/5072 ,  G06F17/5081 ,  H01L21/265 ,  H01L21/8238 ,  H01L27/0629 ,  H02J7/0044 ,  H02J7/025

Abstract: A method for adding a low TCR resistor to a baseline CMOS manufacturing flow. A method of forming a low TCR resistor in a CMOS manufacturing flow. A method of forming an n-type and a p-type transistor with a low TCR resistor in a CMOS manufacturing flow.

Abstract translation: 一种将低TCR电阻添加到基准CMOS制造流程的方法。 在CMOS制造流程中形成低TCR电阻器的方法。 在CMOS制造流程中形成具有低TCR电阻器的n型和p型晶体管的方法。

公开(公告)号：US20140183658A1

公开(公告)日：2014-07-03

申请号：US14074831

申请日：2013-11-08

Applicant: Texas Instruments Incorporated

Inventor： Kamel BENAISSA

IPC: H01L27/06 ,  H01L29/43

CPC classification number: H01L27/0629 ,  H01L27/0288 ,  H01L27/1112 ,  H01L28/20 ,  H01L29/435 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7843

Abstract: An integrated circuit containing a metal gate transistor and a thin polysilicon resistor may be formed by forming a first layer of polysilicon and removed it in an area for the thin polysilicon resistor. A second layer of polysilicon is formed over the first layer of polysilicon and in the area for the thin polysilicon resistor. The thin polysilicon resistor is formed in the second layer of polysilicon and the sacrificial gate is formed in the first layer of polysilicon and the second layer of polysilicon. A PMD layer is formed over the second layer of polysilicon and a top portion of the PMD layer is removed so as to expose the sacrificial gate but not expose the second layer of polysilicon in the thin polysilicon resistor. The sacrificial gate is removed and a metal replacement gate is formed.

Abstract translation: 可以通过形成第一多晶硅层并将其去除在薄多晶硅电阻器的区域中来形成包含金属栅极晶体管和薄多晶硅电阻器的集成电路。 第二层多晶硅形成在多晶硅的第一层上，并在多晶硅薄膜的区域中形成。 薄多晶硅电阻器形成在第二层多晶硅中，并且牺牲栅极形成在第一多晶硅层和第二多晶硅层中。 在第二多晶硅层上形成PMD层，并且去除PMD层的顶部，以暴露牺牲栅极，但不暴露薄多晶硅电阻器中的第二层多晶硅。 去除牺牲栅极并形成金属替换栅极。

公开(公告)号：US20150171077A1

公开(公告)日：2015-06-18

申请号：US14569932

申请日：2014-12-15

Applicant: Texas Instruments Incorporated

Inventor： Kamel BENAISSA

IPC: H01L27/06 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L27/0288 ,  H01L27/1112 ,  H01L28/20 ,  H01L29/435 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7843

Abstract: An integrated circuit containing a metal gate transistor and a thin polysilicon resistor may be formed by forming a first layer of polysilicon and removed it in an area for the thin polysilicon resistor. A second layer of polysilicon is formed over the first layer of polysilicon and in the area for the thin polysilicon resistor. The thin polysilicon resistor is formed in the second layer of polysilicon and the sacrificial gate is formed in the first layer of polysilicon and the second layer of polysilicon. A PMD layer is formed over the second layer of polysilicon and a top portion of the PMD layer is removed so as to expose the sacrificial gate but not expose the second layer of polysilicon in the thin polysilicon resistor. The sacrificial gate is removed and a metal replacement gate is formed.

Abstract translation: 可以通过形成第一多晶硅层并将其去除在薄多晶硅电阻器的区域中来形成包含金属栅极晶体管和薄多晶硅电阻器的集成电路。 第二层多晶硅形成在多晶硅的第一层上，并在多晶硅薄膜的区域中形成。 薄多晶硅电阻器形成在第二层多晶硅中，并且牺牲栅极形成在第一多晶硅层和第二多晶硅层中。 在第二多晶硅层上形成PMD层，并且去除PMD层的顶部，以暴露牺牲栅极，但不暴露薄多晶硅电阻器中的第二层多晶硅。 去除牺牲栅极并形成金属替换栅极。

公开(公告)号：US20140227859A1

公开(公告)日：2014-08-14

申请号：US14220693

申请日：2014-03-20

Applicant: Texas Instruments Incorporated

Inventor： Kamel BENAISSA ,  Amitava CHATTERJEE

IPC: H01L21/761

CPC classification number: H01L21/761 ,  H01L21/266 ,  H01L21/823493 ,  H01L27/0629 ,  H01L27/0802 ,  H01L29/66166 ,  H01L29/8605

Abstract: Integrated circuits and manufacturing methods are presented for creating diffusion resistors (101, 103) in which the diffusion resistor well is spaced from oppositely doped wells to mitigate diffusion resistor well depletion under high biasing so as to provide reduced voltage coefficient of resistivity and increased breakdown voltage for high-voltage applications.

Abstract translation: 提出了用于产生扩散电阻器（101,103）的集成电路和制造方法，其中扩散电阻器阱与相对掺杂的阱间隔开，以在高偏压下减轻扩散电阻器良好的耗尽，从而提供降低的电阻率电压系数和增加的击穿电压 适用于高压应用。