公开(公告)号：US20160061877A1

公开(公告)日：2016-03-03

申请号：US14474012

申请日：2014-08-29

Applicant: Texas Instruments Incorporated

Inventor： Andrew Marshall ,  Ping Jiang

IPC: G01R31/02 ,  G01R27/26

CPC classification number: G01R31/028 ,  G01R27/2605 ,  G01R31/003

Abstract: A method of evaluating at least one parameter of a first capacitor. The method couples a number of capacitors in a capacitor network to a common node, the number of capacitors comprising at least three capacitors. Further, the method first applies a first voltage range to the capacitor network for causing a first voltage drop across the first capacitor, and it evaluates the at least one parameter in response to the first voltage range. The method second applies a second voltage range to the capacitor network for causing a second voltage drop across the first capacitor, the second voltage drop greater than the first voltage drop, and it evaluates the at least one parameter in response to the second voltage range.

Abstract translation: 一种评估第一电容器的至少一个参数的方法。 该方法将电容器网络中的多个电容器耦合到公共节点，电容器的数量包括至少三个电容器。 此外，该方法首先对电容器网络施加第一电压范围，以引起跨越第一电容器的第一电压降，并且响应于第一电压范围来评估该至少一个参数。 该方法二次将电压网络施加第二电压范围，以使第一电容器两端产生第二电压降，第二电压降大于第一电压降，并且响应于第二电压范围评估该至少一个参数。

公开(公告)号：US10453700B2

公开(公告)日：2019-10-22

申请号：US14973973

申请日：2015-12-18

Applicant: Texas Instruments Incorporated

Inventor： Ping Jiang ,  David Gerald Farber

IPC: H01L21/311 ,  H01L21/3105 ,  H01L21/768

Abstract: A method of forming an interconnect structure for an integrated circuit. A dielectric stack is formed on the substrate including an etch-stop layer, a low-k or ULK dielectric layer, and a hard mask layer. The low-k or ULK dielectric is etched using at least two etching processes wherein each etching process is followed by an etch repair process where the etch repair process includes flowing at least one hydrocarbon into the reactor and generating a plasma. The photoresist may be removed using at least two ashing processes wherein each ashing process is followed by an ash repair process where the etch repair process includes flowing at least one hydrocarbon into the reactor and generating a plasma.

公开(公告)号：US09678132B2

公开(公告)日：2017-06-13

申请号：US14474012

申请日：2014-08-29

Applicant: Texas Instruments Incorporated

Inventor： Andrew Marshall ,  Ping Jiang

IPC: G01R31/02 ,  G01R27/26 ,  G01R31/00

CPC classification number: G01R31/028 ,  G01R27/2605 ,  G01R31/003

Abstract: A method of evaluating at least one parameter of a first capacitor. The method couples a number of capacitors in a capacitor network to a common node, the number of capacitors comprising at least three capacitors. Further, the method first applies a first voltage range to the capacitor network for causing a first voltage drop across the first capacitor, and it evaluates the at least one parameter in response to the first voltage range. The method second applies a second voltage range to the capacitor network for causing a second voltage drop across the first capacitor, the second voltage drop greater than the first voltage drop, and it evaluates the at least one parameter in response to the second voltage range.

公开(公告)号：US20170148634A1

公开(公告)日：2017-05-25

申请号：US15287889

申请日：2016-10-07

Applicant: Texas Instruments Incorporated

Inventor： David Gerald Farber ,  Ping Jiang ,  Brian K. Kirkpatrick ,  Douglas T. Grider, III

IPC: H01L21/28 ,  H01L21/8234 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/311

CPC classification number: H01L21/28123 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/32136 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823462

Abstract: A method of manufacturing a semiconductor includes applying a planarization material to a substrate and forming an opening in the planarization material. The opening is filled with polysilicon. A plurality of etching modulation sequences are applied to the substrate, each of the etching modulation sequences including: applying a first etching process to the substrate, wherein the first etching process is more selective to polysilicon than the planarization material; and applying a second etching process to the substrate, wherein the second etching process is more selective to the planarization material than the polysilicon.

公开(公告)号：US09881795B2

公开(公告)日：2018-01-30

申请号：US15287889

申请日：2016-10-07

Applicant: Texas Instruments Incorporated

Inventor： David Gerald Farber ,  Ping Jiang ,  Brian K. Kirkpatrick ,  Douglas T. Grider, III

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/321 ,  H01L21/8234

CPC classification number: H01L21/28123 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/32136 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823462

Abstract: A method of manufacturing a semiconductor includes applying a planarization material to a substrate and forming an opening in the planarization material. The opening is filled with polysilicon. A plurality of etching modulation sequences are applied to the substrate, each of the etching modulation sequences including: applying a first etching process to the substrate, wherein the first etching process is more selective to polysilicon than the planarization material; and applying a second etching process to the substrate, wherein the second etching process is more selective to the planarization material than the polysilicon.

公开(公告)号：US09490143B1

公开(公告)日：2016-11-08

申请号：US14952693

申请日：2015-11-25

Applicant: Texas Instruments Incorporated

Inventor： David Gerald Farber ,  Ping Jiang ,  Brian K. Kirkpatrick ,  Douglas T. Grider, III

IPC: H01L21/3205 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/02

CPC classification number: H01L21/28123 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/32136 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823462

Abstract: A method of manufacturing a semiconductor includes applying a planarization material to a substrate and forming an opening in the planarization material. The opening is filled with polysilicon. A plurality of etching modulation sequences are applied to the substrate, each of the etching modulation sequences including: applying a first etching process to the substrate, wherein the first etching process is more selective to polysilicon than the planarization material; and applying a second etching process to the substrate, wherein the second etching process is more selective to the planarization material than the polysilicon.

Abstract translation: 制造半导体的方法包括将平坦化材料施加到基板并在平坦化材料中形成开口。 开口充满了多晶硅。 多个蚀刻调制序列被施加到衬底，每个蚀刻调制序列包括：对衬底施加第一蚀刻工艺，其中第一蚀刻工艺比平坦化材料对多晶硅更有选择性; 以及对所述衬底施加第二蚀刻工艺，其中所述第二蚀刻工艺对所述平坦化材料比所述多晶硅更具选择性。