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1.发明公开公开(公告)号：US20230353185A1
公开(公告)日：2023-11-02
申请号：US17730451
申请日：2022-04-27
Applicant: Texas Instruments Incorporated
Inventor： Deep Banerjee , Lokesh Kumar Gupta , Madhulatha Bonu , Vikas Thawani
CPC classification number: H04B1/405 , H04B1/44 , H04B1/0458 , H04B2001/0408
Abstract: A controller area network including one or more first network nodes biased from a first power supply voltage, and a second network node biased from a second, lower, power supply voltage. The second network node includes a transmitter driving a differential voltage onto bus lines to communicate a dominant bus state at a second dominant state common mode voltage, a receiver coupled to the bus lines, sense circuitry to sense a common mode voltage at the bus lines, and control circuitry to control a recessive state common mode voltage in response to the sensed dominant state common mode voltage.
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公开(公告)号：US20180006856A1
公开(公告)日：2018-01-04
申请号：US15200706
申请日：2016-07-01
Applicant: Texas Instruments Incorporated
CPC classification number: H04L27/22 , H03D3/00 , H03K19/21 , H03L7/081 , H03L7/087 , H03L7/113 , H04L7/0087 , H04L7/0331 , H04L27/2271
Abstract: Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase; when the data signal is oscillating at the first phase, output a first logic value; and when the data signal is oscillating at the second phase, output a second logic value, the output of the fast phase change detection circuit being used to determine whether the first output signal or the second output signal will be utilized in the feedback loop of the low bandwidth phase lock loop.
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公开(公告)号：US10728068B2
公开(公告)日：2020-07-28
申请号：US15860988
申请日：2018-01-03
Applicant: Texas Instruments Incorporated
IPC: H04L27/22 , H03D3/00 , H03L7/081 , H04L27/227 , H03K19/21 , H03L7/087 , H03L7/113 , H04L7/033 , H04L7/00
Abstract: Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase.
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4.发明申请公开(公告)号：US20140247175A1
公开(公告)日：2014-09-04
申请号：US14194281
申请日：2014-02-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Udayan Dasgupta , Janakiraman S , Ganesan Thiagarajan , Abhijit A. Patki , Madhulatha Bonu , Venugopal Gopinathan
CPC classification number: H03M1/125 , H03M1/08 , H03M1/0836 , H03M1/0845 , H03M1/0854 , H03M1/089 , H03M1/124 , H03M1/1265 , H03M1/186 , H03M1/36
Abstract: A method, comprising: receiving a plurality of 2-tuples of asynchronously sampled inputs at an asynchronous to synchronous reconstructor; performing a coarse asynchronous to synchronous conversion using the plurality of 2-tuples to generate a plurality of low precision synchronous outputs; generating a high precision synchronous output, z0, using a plurality of asynchronous 2-tuples, low precision synchronous outputs after it, and its own high precision outputs from previous steps; calculating c0 and c−1 by summing future low precision outputs and the past high precision outputs after they are weighted with the appropriate windowed sinc. values and then subtracted from appropriate asynchronous samples; calculating, the four quantities “s−11”, “s01”, “s00” and “s−10” based on particular values of the windowed sinc. function; and using c0, c−1, s−11, s01, s00 and s−10, the high precision synchronous output of interest, z0 is generated.
Abstract translation: 一种方法，包括：在异步同步重构器处接收多个异步采样输入的2元组; 使用所述多个2元组执行粗略的异步到同步转换，以产生多个低精度同步输出; 使用多个异步2元组，其后的低精度同步输出以及自己的高精度输出从前面的步骤产生高精度同步输出z0; 通过将未来的低精度输出和过去的高精度输出相加后，使用适当的加窗sinc来计算c0和c-1。 值，然后从适当的异步采样中减去; 基于窗口的sinc的特定值计算四个量“s-11”，“s01”，“s00”和“s-10”。 功能; 并使用c0，c-1，s-11，s01，s00和s-10，生成高精度的同步输出z0。
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5.发明申请公开(公告)号：US20140247171A1
公开(公告)日：2014-09-04
申请号：US14194181
申请日：2014-02-28
Applicant: Texas Instruments Incorporated
Inventor： Janakiraman S. , Udayan Dasgupta , Ganesan Thiagarajan , Abhijit A. Patki , Madhulatha Bonu , Venugopal Gopinathan
CPC classification number: H03M1/125 , H03M1/08 , H03M1/0836 , H03M1/0845 , H03M1/0854 , H03M1/089 , H03M1/124 , H03M1/1265 , H03M1/186 , H03M1/36
Abstract: A method, comprising: receiving an analog input; determining an upper outer rail and a lower outer rail as polling values to be used by voltage comparators; blanking at least three comparators; determining which two of the at least three comparators are closest to the input analog voltage levels; defining the two comparators which are closest to the analog input signal to be the next comparators of the next sampling process; assigning a remaining comparator at a voltage level in between the new top and bottom voltage levels; enabling the outer rails, but blanking the inner rail; progressively narrowing down the voltage range spanned by the two outer comparators; and generating a 2-tuple value of an asynchronous voltage comparator crossing.
Abstract translation: 一种方法，包括：接收模拟输入; 确定上部外轨道和下部外部轨道作为要由电压比较器使用的轮询值; 至少阻止三位比较人; 确定所述至少三个比较器中的哪两个最接近所述输入模拟电压电平; 将最接近模拟输入信号的两个比较器定义为下一个采样过程的下一个比较器; 将剩余比较器分配在新的顶部和底部电压电平之间的电压电平; 使得外轨能够消除内轨; 逐渐缩小两个外部比较器跨越的电压范围; 并产生异步电压比较器杂交的2元组值。
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Patent Agency Ranking
6.发明申请公开(公告)号：US20200313945A1
公开(公告)日：2020-10-01
申请号：US16900010
申请日：2020-06-12
Applicant: Texas Instruments Incorporated
Abstract: Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase.
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公开(公告)号：US10014844B1
公开(公告)日：2018-07-03
申请号：US15395353
申请日：2016-12-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Kumar Anurag Shrivastava , Subhashish Mukherjee , Madhulatha Bonu
Abstract: A circuit includes an amplifier having an input that receives an alternating current (AC) waveform and an output that is coupled to a power source via a bias resistor. A bulk acoustic wave (BAW) resonator is coupled in parallel to the bias resistor via the power source and the amplifier output. The BAW resonator and the amplifier output forms a band pass filter to filter the AC waveform received at the amplifier input and to provide a filtered AC waveform at the amplifier output.
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公开(公告)号：US09893916B2
公开(公告)日：2018-02-13
申请号：US15200706
申请日：2016-07-01
Applicant: Texas Instruments Incorporated
CPC classification number: H04L27/22 , H03D3/00 , H03K19/21 , H03L7/081 , H03L7/087 , H03L7/113 , H04L7/0087 , H04L7/0331 , H04L27/2271
Abstract: Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase; when the data signal is oscillating at the first phase, output a first logic value; and when the data signal is oscillating at the second phase, output a second logic value, the output of the fast phase change detection circuit being used to determine whether the first output signal or the second output signal will be utilized in the feedback loop of the low bandwidth phase lock loop.
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9.发明授权公开(公告)号：US12255680B2
公开(公告)日：2025-03-18
申请号：US17730451
申请日：2022-04-27
Applicant: Texas Instruments Incorporated
Inventor： Deep Banerjee , Lokesh Kumar Gupta , Madhulatha Bonu , Vikas Thawani
Abstract: A controller area network including one or more first network nodes biased from a first power supply voltage, and a second network node biased from a second, lower, power supply voltage. The second network node includes a transmitter driving a differential voltage onto bus lines to communicate a dominant bus state at a second dominant state common mode voltage, a receiver coupled to the bus lines, sense circuitry to sense a common mode voltage at the bus lines, and control circuitry to control a recessive state common mode voltage in response to the sensed dominant state common mode voltage.
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公开(公告)号：US10483909B2
公开(公告)日：2019-11-19
申请号：US15173044
申请日：2016-06-03
Applicant: Texas Instruments Incorporated
Inventor： Subhashish Mukherjee , Kumar Anurag Shrivastava , Madhulatha Bonu
Abstract: Methods and apparatus are disclosed to generate an oscillating output signal having a voltage swing greater than a voltage swing across nodes of active devices. An example oscillator includes a tank to generate an oscillating output signal in response receiving an edge of an enable signal; a feedback generator including a first gain stage forming a first feedback loop with the tank, the first feedback loop providing a first charge to maintain the oscillating output signal and a second gain stage forming a second feedback loop with the tank, the second feedback loop providing a second charge to maintain the oscillating output signal, the first and second charges combining with the oscillating output signal to generate a high voltage swing; and an attenuator connected between the tank and the feedback generator to isolate the tank from active components of the feedback generator.
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