公开(公告)号：US10475514B2

公开(公告)日：2019-11-12

申请号：US15976315

申请日：2018-05-10

申请人： The Penn State Research Foundation

发明人： Xueqing Li ,  Sumitha George ,  John Sampson ,  Sumeet Gupta ,  Suman Datta ,  Vijaykrishnan Narayanan ,  Kaisheng Ma

IPC分类号： G11C14/00 ,  G11C13/00 ,  H01L29/78 ,  G11C11/16 ,  G11C11/22

摘要： Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the IDS-VG hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two IDS states at VG=0.

公开(公告)号：US20180330791A1

公开(公告)日：2018-11-15

申请号：US15976315

申请日：2018-05-10

申请人： The Penn State Research Foundation

发明人： Xueqing Li ,  Sumitha George ,  John Sampson ,  Sumeet Gupta ,  Suman Datta ,  Vijaykrishnan Narayanan ,  Kaisheng Ma

IPC分类号： G11C14/00 ,  H01L29/78 ,  G11C13/00

CPC分类号： G11C14/0072 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/223 ,  G11C11/2275 ,  G11C11/2293 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0061 ,  G11C13/0069 ,  G11C14/0054 ,  G11C14/0081 ,  G11C14/009 ,  H01L29/78391

摘要： Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the IDS−VG hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two IDS states at VG=0.

公开(公告)号：US10672475B2

公开(公告)日：2020-06-02

申请号：US16580256

申请日：2019-09-24

申请人： The Penn State Research Foundation

发明人： Xueqing Li ,  Sumitha George ,  John Sampson ,  Sumeet Gupta ,  Suman Datta ,  Vijaykrishnan Narayanan ,  Kaisheng Ma

IPC分类号： G11C14/00 ,  G11C13/00 ,  G11C11/22 ,  H01L29/78 ,  G11C11/16

摘要： Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the IDS−VG hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two IDS states at VG=0.

公开(公告)号：US20200027508A1

公开(公告)日：2020-01-23

申请号：US16580256

申请日：2019-09-24

申请人： The Penn State Research Foundation

发明人： Xueqing Li ,  Sumitha George ,  John Sampson ,  Sumeet Gupta ,  Suman Datta ,  Vijaykrishnan Narayanan ,  Kaisheng Ma

IPC分类号： G11C14/00 ,  G11C13/00 ,  G11C11/22 ,  G11C11/16 ,  H01L29/78

摘要： Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the IDS−VG hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two IDS states at VG=0.